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參數(shù)資料
| 型號： | csdpram |
| 廠商： | Altera Corporation |
| 英文描述： | Parameterized Cycle-Shared Dual-Port RAM(參數(shù)確定的周期共享雙端口隨機存儲器) |
| 中文描述： | 參數(shù)化周期共享雙口RAM（參數(shù)確定的周期共享雙端口隨機存儲器） |
| 文件頁數(shù)： | 36/48頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CSDPRAM |
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Altera Corporation
31
Storage Functions
lpm_ram_io
Parameterized Random Access Memory
with a Single I/ O Port
The
lpm_ram_io
function can be used as
either synchronous or asynchronous
random access memory. The
lpm_ram_io
function has a bidirectional bus.
Ports
Name
Type
Required
Description
address[]
Input
Yes
Address input to the memory. This port is
LPM_WIDTHAD
wide. If
memenab
is
used, it should be inactive when
address[]
is changing.
Synchronizes memory loading. If the
inclock
port is used, the
we
port acts as
an enable for write operations synchronized to the rising edge of the
inclock
input. If the
inclock
port is not used, the
we
port acts as an enable for
asynchronous write operations.
Synchronizes
dio[]
from memory. The addressed memory content
q[]
response is synchronous when the
outclock
port is connected, and
asynchronous when it is not connected.
Write enable input. Either
we
or
outenab
should be used. When high, enables
write operations to the memory. If no clock ports are used, the data on the
address[]
port should not change when
we
is high (1). Required if
clock
is
not present. If
we
is absent, the default value is enabled.
Output enable input. High (1):
dio[]
from memory
address[]
. Low (0):
Memory
address[]
from
dio[]
. Either
memenab
or
outenab
must be
present.
Memory output tri-state enable. Either
memenab
or
outenab
must be
connected. If
memenab
is present, it should be inactive when
address[]
is
changing.
Data port for the memory. This port is
LPM_WIDTH
wide.
inclock
Input
No
outclock
Input
No
we
Input
Yes
outenab
Input
No
memenab
Input
No
dio[]
Bidirectional
Yes
LPM_RAM_IO
address[]
inclock
outclock
we
outenab
memenab
LPM_ADDRESS_CONTROL=
LPM_FILE=
LPM_INDATA=
LPM_NUMWORDS=
LPM_OUTDATA="UNREGISTERED"
LPM_WIDTH=
LPM_WIDTHAD=
dio[]
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