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參數(shù)資料
| 型號(hào)： | csdpram |
| 廠商： | Altera Corporation |
| 英文描述： | Parameterized Cycle-Shared Dual-Port RAM(參數(shù)確定的周期共享雙端口隨機(jī)存儲(chǔ)器) |
| 中文描述： | 參數(shù)化周期共享雙口RAM（參數(shù)確定的周期共享雙端口隨機(jī)存儲(chǔ)器） |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CSDPRAM |
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Altera Corporation
19
Arithmetic Functions
lpm_compare
Parameterized Comparator
Ports
Name
Type
Required
Description
dataa[]
Input
Input
Input
Yes
Yes
No
The
datab[]
signal is compared to this value. This port is
LPM_WIDTH
wide.
Value to be compared to
dataa[]
. This port is
LPM_WIDTH
wide.
Clock for pipelined usage. The
clock
port provides pipelined operation for
lpm_compare
. For
LPM_PIPELINE
values other than 0 (default value), the
clock
port must be connected.
Asynchronous clear for pipelined usage. The pipeline initializes to undefined.
The
aclr
port can be used at any time to reset the pipeline to all 0s,
clock
.
High (1) if
dataa[]
<
datab[]
. One of the
alb
,
aeb
,
agb
,
ageb
,
aleb
, or
aneb
outputs must be present.
High (1) if
dataa[]
=
datab[]
. One of the
alb
,
aeb
,
agb
,
ageb
,
aleb
, or
aneb
outputs must be present.
High (1) if
dataa[]
>
datab[]
. One of the
alb
,
aeb
,
agb
,
ageb
,
aleb
, or
aneb
outputs must be present.
High (1) if
dataa[]
≥
datab[]
. One of the
alb
,
aeb
,
agb
,
ageb
,
aleb
, or
aneb
outputs must be present.
High (1) if
dataa[]
≠
datab[]
. One of the
alb
,
aeb
,
agb
,
ageb
,
aleb
, or
aneb
outputs must be present.
High (1) if
dataa[]
≤
datab[]
. One of the
alb
,
aeb
,
agb
,
ageb
,
aleb
, or
aneb
outputs must be present.
datab[]
clock
aclr
Input
No
alb
Output
No
aeb
Output
No
agb
Output
No
ageb
Output
No
aneb
Output
No
aleb
Output
No
dataa[]
datab[]
clock
aclr
LPM_COMPARE
alb
aeb
agb
ageb
aneb
aleb
CHAIN_SIZE=
LPM_PIPELINE=
LPM_REPRESENTATION=
LPM_WIDTH=
ONE_INPUT_IS_CONSTANT=
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