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參數(shù)資料
| 型號(hào)： | csdpram |
| 廠商： | Altera Corporation |
| 英文描述： | Parameterized Cycle-Shared Dual-Port RAM(參數(shù)確定的周期共享雙端口隨機(jī)存儲(chǔ)器) |
| 中文描述： | 參數(shù)化周期共享雙口RAM（參數(shù)確定的周期共享雙端口隨機(jī)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 28/48頁(yè) |
| 文件大?。?/td> | 293K |
| 代理商： | CSDPRAM |
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Altera Corporation
23
Arithmetic Functions
lpm_mult
Parameterized Multiplier
The
lpm_mult
function allows two
signed or unsigned numbers to be
multiplied. In addition, the result of
the multiplication can be added to a
third number.
Ports
Name
Type
Required
Description
clock
Input
No
Clock for pipelined usage. The
clock
port provides pipelined operation for
lpm_mult
. For
LPM_PIPELINE
values other than 0 (default value), the
clock
port must be connected.
Multiplicand. This port is
LPM_WIDTHA
wide.
Partial sum. This port is
LPM_WIDTHS
wide.
Multiplier. This port is
LPM_WIDTHB
wide.
Asynchronous clear for pipelined usage. The pipeline initializes to undefined.
The
aclr
port can be used at any time to reset the pipeline to all 0s,
asynchronously to
clock
.
This port is
LPM_WIDTHP
wide. If
LPM_WIDTHP
< max (
LPM_WIDTHA
+
LPM_WIDTHB,
LPM_WIDTHS
) or
(
LPM_WIDTHS)
, only the
LPM_WIDTHP
MSBs are present.
dataa[]
Input
Input
Input
Input
Yes
No
Yes
No
sum[]
datab[]
aclr
result[]
Output
Yes
LPM_MULT
result[]
dataa[]
sum[]
datab[]
aclr
INPUT_A_IS_CONSTANT=
INPUT_B_IS_CONSTANT=
LPM_PIPELINE=
LPM_REPRESENTATION=
LPM_WIDTHA=
LPM_WIDTHB=
LPM_WIDTHP=(LPM_WIDTHA+LPM_WIDTHB)
LPM_WIDTHS=LPM_WIDTHA
clock
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