參數(shù)資料
型號(hào)： csdpram
廠商： Altera Corporation
英文描述： Parameterized Cycle-Shared Dual-Port RAM(參數(shù)確定的周期共享雙端口隨機(jī)存儲(chǔ)器)
中文描述： 參數(shù)化周期共享雙口RAM（參數(shù)確定的周期共享雙端口隨機(jī)存儲(chǔ)器）
文件頁(yè)數(shù)： 13/48頁(yè)
文件大?。?/td> 293K
代理商： CSDPRAM
8
Altera Corporation
Gate Functions
lpm_decode
Parameterized Decoder
Ports
Parameters
Name
Type
Required
Description
clock
Input
No
Clock for pipelined usage. The
clock
port provides pipelined operation for
lpm_decode
. For
LPM_PIPELINE
values other than 0 (default value), the
clock
port must be connected.
Asynchronous clear for pipelined usage. The pipeline initializes to undefined.
The
aclr
port can be used at any time to reset the pipeline to all 0s,
asynchronously to the clock.
Data input. Treated as an unsigned binary-encoded number. This port is
LPM_WIDTH
wide.
Enable. All outputs are low when this port is inactive. If absent, the default
value is active (high).
Output of the decoder. This port is
LPM_DECODES
wide.
If
data[]
≥
LPM_DECODES
, all
eq[]
outputs are 0.
aclr
Input
No
data[]
Input
Yes
enable
Input
No
eq[]
Output
Yes
Name
Required
Value
Description
LPM_DECODES
Yes
2
LPM_WIDTH
≥
Integer > 0 Number of explicit decoder outputs. The default value is
2
LPM_WIDTH
.
Integer
≥
0
Specifies the number of clock cycles of latency associated with
the
eq[]
output. A value of zero (0) indicates that no latency
exists, and that a purely combinatorial function will be
instantiated. The default value is 0 (non-pipelined).
Integer > 0
Width of the input value to be decoded.
LPM_PIPELINE
No
LPM_WIDTH
Yes
LPM_DECODE
LPM_DECODES=2^LPM_WIDTH
LPM_PIPELINE=
LPM_WIDTH=
eq[]
clock
aclr
data[]
enable
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