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參數資料
| 型號： | csdpram |
| 廠商： | Altera Corporation |
| 英文描述： | Parameterized Cycle-Shared Dual-Port RAM(參數確定的周期共享雙端口隨機存儲器) |
| 中文描述： | 參數化周期共享雙口RAM（參數確定的周期共享雙端口隨機存儲器） |
| 文件頁數： | 33/48頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CSDPRAM |
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28
Altera Corporation
Storage Functions
lpm_latch
Parameterized Latch
Ports
Parameters
Name
Type
Required
Description
aset
Input
No
Asynchronous set input. Default = 0. Sets
q[]
outputs to the value specified
by
LPM_AVALUE
, if that value is present. If no
LPM_AVALUE
is specified,
aset
will set the count to all 1s. If both
aset
and
aclr
are used and both are
asserted,
aclr
is dominant. The
aset
and
aclr
inputs affect the output
q[]
values before polarity is applied to the ports.
Data input to the D-type latch. This port is
LPM_WIDTH
wide. If the
data[]
port is not used, either
aset
or
aclr
must be used.
Latch enable input. High = flow-through, low = latch.
This port is provided only for backwards-compatibility in MAX+PLUS II
pre-version 6.0 designs. Altera does not recommend using this port in new
designs.
Asynchronous clear input. Default = 0. Sets the latch to all 0s. If both
aset
and
aclr
are used and both are asserted,
aclr
is dominant. The
aset
and
aclr
inputs affect the output
q[]
values before the polarity is applied to the
ports.
Data output from the latches. This port is
LPM_WIDTH
wide.
data[]
Input
No
gate
Input
Input
Yes
No
aconst
aclr
Input
No
q[]
Output
Yes
Name
Required
Value
Description
LPM_WIDTH
Yes
No
Integer > 0
Integer
≥
0
Width of the
data[]
and
q[]
ports.
Constant value that is loaded when
aset
is high. The default
value of
LPM_AVALUE
is all 1s.
LPM_AVALUE
LPM_LATCH
aset
data[]
gate
aconst
aclr
LPM_WIDTH=
LPM_AVALUE=
q[]
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