1.2.4 Serial Port Interface The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, S" />
參數(shù)資料
型號(hào)： CS5528-ASZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 18/56頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 8CH 24-SSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 14.8mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 24-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極
CS5521/22/23/24/28
DS317F8
25
1.2.4 Serial Port Interface
The CS5521/22/23/24/28’s serial interface consists
of four control lines: CS, SCLK, SDI, SDO.
Figure 10 illustrates the serial sequence necessary
to write to, or read from the serial port’s registers.
CS (Chip Select) is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three-wire interface.
SDI (Serial Data In) is the data signal used to trans-
fer data to the converters.
SDO (Serial Data Out) is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
SCLK (Serial Clock) is the serial bit clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic. To accommodate opto-isolators SCLK
is designed with a Schmitt-trigger input to allow an
opto-isolator with slower rise and fall times to di-
rectly drive the pin. Additionally, SDO is capable
of sinking or sourcing up to 5 mA to directly drive
an opto-isolator LED. SDO will have less than a
400 mV loss in the drive voltage when sinking or
sourcing 5 mA.
Command Time
8SCLKs
Data Time 24 SCLKs
Write Cycle
CS
SCLK
SDI
MSB
LSB
Command Time
8SCLKs
CS
SCLK
SDI
Data Time 24 SCLKs
SDO
MSB
LSB
Read Cycle
Command Time
8 SCLKs
8 SCLKs Clear SDO Flag
SDO
SCLK
SDI
Data Time
24 SCLKs
MSB
LSB
* td = XIN/OWR clock cycles for each conversion except the
first conversion which will take XIN/OWR + 7 clock cycles
XIN/OWR
Clock Cycles
t *
d
Figure 10. Command and Data Word Timing
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