參數(shù)資料
型號： CS5528-ASZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 1/56頁
文件大小： 0K
描述： IC ADC 24BIT 8CH 24-SSOP
標(biāo)準包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 14.8mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 24-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，單極；8 個單端，雙極
Copyright
Cirrus Logic, Inc. 2009
(All Rights Reserved)
CS5521/22/23/24/28
16-bit or 24-bit, 2/4/8-channel ADCs with PGIA
Features
Low Input Current (100 pA), Chopper-
stabilized Instrumentation Amplifier
Scalable Input Span (Bipolar/Unipolar)
- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,
2.5 V, 5 V
- External: 10 V, 100 V
Wide VREF Input Range (+1 to +5 V)
Fourth Order Delta-Sigma A/D Converter
Easy to Use Three-wire Serial Interface Port
- Programmable/Auto Channel Sequencer with
Conversion Data FIFO
- Accessible Calibration Registers per Channel
- Compatible with SPI and Microwire
System and Self Calibration
Eight Selectable Word Rates
- Up to 617 Sps (XIN = 200 kHz)
- Single Conversion Settling
- 50/60 Hz ±3 Hz Simultaneous Rejection
Single +5 V Power Supply Operation
- Charge Pump Drive for Negative Supply
- +3 to +5 V Digital Supply Operation
Low Power Consumption: 6.0 mW
General Description
The CS5521/22/23/24/28 are highly integrated
ΔΣ ana-
log-to-digital converters (ADCs) which use charge-
balance techniques to achieve 16-bit (CS5521/23) and
24-bit (CS5522/24/28) performance. The ADCs come as
either
two-channel
(CS5521/22),
four-channel
(CS5523/24), or eight-channel (CS5528) devices and
include a low-input-current, chopper-stabilized instru-
mentation amplifier. To permit selectable input spans of
25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs
include a PGA (programmable gain amplifier). To ac-
commodate ground-based thermocouple applications,
the devices include a charge pump drive which provides
a negative bias voltage to the on-chip amplifiers.
These devices also include a fourth-order
ΔΣ modulator
followed by a digital filter which provides eight selectable
output word rates. The digital filters are designed to settle
to full accuracy within one conversion cycle and when
operated at word rates below 30 Sps, they reject both
50 Hz and 60 Hz interference.
These single-supply products are ideal solutions for
measuring isolated and non-isolated, low-level signals in
process control applications.
ORDERING INFORMATION
VA+
AGND
VREF+ VREF-
VD+
DGND
XIN XOUT
NBV
Latch
Differential
Digital Filter
4th Order
ΔΣ
Modulator
Clock
Gen.
MUX
AIN2+
X1
X1
CS5524
Shown
AIN2-
AIN1+
AIN1-
AIN4+
AIN4-
AIN3+
AIN3-
A0 A1
CPD
Controller,
Pr
og
ra
mma
b
le
Gai
n
Setup Registers,
&
Data FIFO &
Calibration Registers
Channel Scan
Logic
Serial Port
Interface
+
X20
SDO
SDI
SCLK
CS
JUL ‘09
DS317F8
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