參數(shù)資料
型號： COP8CCR9LVA8
廠商： National Semiconductor
文件頁數(shù)： 78/111頁
文件大小： 0K
描述： IC MCU EEPROM 8BIT 68-PLCC
標準包裝： 18
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 59
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
其它名稱： *COP8CCR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
The A/D Converter is supported by three memory mapped registers: two result registers and the control
register. When the device is reset, the mode control register (ENAD) is cleared, the A/D is powered down
and the A/D result registers have unknown data.
5.14.1.1 A/D Control Register
The control register, ENAD, contains 4 bits for channel selection, 1 bit for mode selection, 1 bit for the
multiplexor output selection, 1 bit for prescaler selection, and a Busy bit. An A/D conversion is initiated by
setting the ADBSY bit in the ENAD control register. The result of the conversion is available to the user in
the A/D result registers, ADRSTH and ADRSTL, when ADBSY is cleared by the hardware on completion
of the conversion.
Table 5-18. ENAD
Bit 7
Bit 0
Channel Select
Mode
Mux/Out
Prescale
Busy
Select
ADCH3
ADCH2
ADCH1
ADCH0
ADMOD
MUX
PSC
ADBSY
5.14.1.1.1 Channel Select
This 4-bit field selects one of sixteen channels to be the VIN+. The mode selection and the mux output
determine the VIN-input. When MUX = 0, all sixteen channels are available, as shown in Table 5-19. When
MUX = 1, only fourteen channels are available, as shown in Table 5-20.
All port pins which are used, in the application, in A/D operations must be configured as high-impedance
inputs. If the ports are configured as outputs or inputs with weak pull-up there will be a conflict between
the analog signal and the digitally driven output.
Table 5-19. A/D Converter Channel Selection when the Multiplexor Output is Disabled
Mode Select
ADMOD = 0
Mux Output
Select Bits
ADMOD = 1
Single Ended
Disabled
Differential Mode
Mode
ADCH3
ADCH2
ADCH1
ADCH0
Channel No.
Channel Pairs (+,
MUX
)
0
0, 1
0
1
1, 0
0
1
0
2
2, 3
0
1
3
3, 2
0
1
0
4
4, 5
0
1
0
1
5
5, 4
0
1
0
6
6, 7
0
1
7
7, 6
0
1
0
8
8, 9
0
1
0
1
9
9, 8
0
1
0
1
0
10
10, 11
0
1
0
1
11
11, 10
0
1
0
12
12, 13
0
1
0
1
13
13, 12
0
1
0
14
14, 15
0
1
15
15, 14
0
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
69
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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