參數(shù)資料
型號(hào)： COP8CCR9LVA8
廠商： National Semiconductor
文件頁數(shù)： 66/111頁
文件大?。?/td> 0K
描述： IC MCU EEPROM 8BIT 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 59
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
其它名稱： *COP8CCR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.12.6 MULTI-INPUT WAKE-UP
The Multi-Input Wake-up feature is used to return (wake-up) the device from either the HALT or IDLE
modes. Alternately Multi-Input Wake-up/Interrupt feature may also be used to generate up to 8 edge
selectable external interrupts.
Figure 5-15 shows the Multi-Input Wake-up logic.
The Multi-Input Wake-up feature utilizes the L Port. The user selects which particular L port bit (or
combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done
through the register WKEN. The register WKEN is an 8-bit read/write register, which contains a control bit
for every L port bit. Setting a particular WKEN bit enables a Wake-up from the associated L port pin.
The user can select whether the trigger condition on the selected L Port pin is going to be either a positive
edge (low to high transition) or a negative edge (high to low transition). This selection is made via the
register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the
control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the
bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in
order to avoid a Wake-up condition as a result of the edge change. First, the associated WKEN bit should
be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be
cleared, followed by the associated WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive
(low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for
an input interrupt. The program would be as follows:
RBIT
5, WKEN
; Disable MIWU
SBIT
5, WKEDG
; Change edge polarity
RBIT
5, WKPND
; Reset pending flag
SBIT
5, WKEN
; Enable MIWU
If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wake-
up/Interrupt, a safety procedure should also be followed to avoid wake-up conditions. After the selected L
port bits have been changed from output to input but before the associated WKEN bits are enabled, the
associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the
associated WKPND bits being cleared.
This same procedure should be used following reset, since the L port inputs are left floating as a result of
reset.
The occurrence of the selected trigger condition for Multi-Input Wake-up is latched into a pending register
called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected
trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending
flags. Since WKPND is a pending register for the occurrence of selected wake-up conditions, the device
will not enter the HALT mode if any Wake-up bit is both enabled and pending. Consequently, the user
must clear the pending flags before attempting to enter the HALT mode.
WKEN and WKEDG are all read/write registers, and are cleared at reset. WKPND register contains
random value after reset.
5.13 USART
The device contains a full-duplex software programmable USART. The USART (Figure 5-16) consists of a
transmit shift register, a receive shift register and seven addressable registers, as follows: a transmit
buffer register (TBUF), a receiver buffer register (RBUF), a USART control and status register (ENU), a
USART receive control and status register (ENUR), a USART interrupt and clock source register (ENUI), a
prescaler select register (PSR) and baud (BAUD) register. The ENU register contains flags for transmit
and receive functions; this register also determines the length of the data frame (7, 8 or 9 bits), the value
of the ninth bit in transmission, and parity selection bits. The ENUR register flags framing, data overrun,
parity errors and line breaks while the USART is receiving.
58
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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