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| 型號： | COP8CCR9LVA8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 58/111頁 |
| 文件大小： | 0K |
| 描述： | IC MCU EEPROM 8BIT 68-PLCC |
| 標準包裝： | 18 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 59 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CCR9LVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
description of these bits.
Table 5-15 lists the valid contents of the four most significant bits of the ITMR Register. Any other value is
illegal. States are presented in the only valid sequence. Any attempt to make a transition to any state
other than an adjacent valid state will be ignored by the logic and the ITMR Register will not be changed.
Table 5-15. Valid Contents of Dual Clock Control Bits
LSON
HSON
DCEN
CCKSEL
Mode
0
1
0
High Speed
1
0
High Speed/Dual Clock Transition
1
0
Dual Clock
1
Dual Clock/Low Speed Transition
1
0
1
Low Speed
5.12.2 OSCILLATOR STABILIZATION
Both the high speed oscillator and low speed oscillator have a startup delay associated with them. When
switching between the modes, the software must ensure that the appropriate oscillator is started up and
stabilized before switching to the new mode. See Table 5-2, Startup Times for approximate startup times
for both oscillators.
5.12.3 HIGH SPEED MODE OPERATION
This mode of operation allows high speed operation for both the main Core clock and also for the Idle
Timer. This is the default mode of the device and will always be entered upon any of the Reset conditions
described in the Reset section. It can also be entered from Dual Clock mode. It cannot be directly entered
from the Low Speed mode without passing through the Dual Clock mode first.
To enter from the Dual Clock mode, the following sequence must be followed using two separate
instructions:
1. Software clears DCEN to 0.
2. Software clears LSON to 0.
5.12.3.1 High Speed Halt Mode
The fully static architecture of this device allows the state of the microcontroller to be frozen. This is
accomplished by stopping the internal clock of the device during the HALT mode. The controller also stops
the CKI pin from oscillating during the HALT mode. The processor can be forced to exit the HALT mode
and resume normal operation at any time.
During normal operation, the actual power consumption depends heavily on the clock speed and operating
voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device
only draws a small leakage current, plus current for the BOR feature (if enabled), plus any current
necessary for driving the outputs. Since total power consumption is affected by the amount of current
required to drive the outputs, all I/Os should be configured to draw minimal current prior to entering the
HALT mode, if possible. In order to reduce power consumption even further, the power supply (VCC) can
be reduced to a very low level during the HALT mode, just high enough to ensure retention of data stored
5.12.3.1.1 Entering The High Speed Halt Mode
The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.
All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to
a very low level.
50
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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