參數(shù)資料
型號： CL-PS7110-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Low-Power System-on-a-Chip
中文描述： MROM, RISC MICROCONTROLLER, PQFP208
封裝： VQFP-208
文件頁數(shù)： 59/82頁
文件大小： 1101K
代理商： CL-PS7110-VC-A
May 1997
59
DATA BOOK v1.5
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
3.2.31 MCEOI — Media Changed End of Interrupt
A write to this location clears the interrupt generated by a rising edge of the MEDCHG input pin.
3.2.32 TEOI — Tick End of Interrupt Location
A write to this location clears the current pending tick interrupt and watchdog interrupt.
3.2.33 TC1EOI TC1 — End of Interrupt Location
A write to this location clears the under-flow interrupt generated by TC1.
3.2.34 TC2EOI TC2 — End Of Interrupt Location
A write to this location clears the under-flow interrupt generated by TC2.
3.2.35 RTCEOI — RTC Match End Of Interrupt
A write to this location clears the RTC match interrupt.
3.2.36 UMSEOI — UART Modem Status Changed End of Interrupt
A write to this location clears the modem status changed interrupt.
3.2.37 COEOI — Codec End of Interrupt Location
A write to this location clears the sound interrupt (CSINT).
3.2.38 HALT — Enter Idle State Location
A write to this location places the system into the idlestate by halting the clock to the processor until an
interrupt is generated. A write to this location while there is an active interrupt has no effect. If the idle
state is entered with no interrupts enabled, there is no mechanism for exiting the state except for a system
reset.
3.2.39 STDBY — Enter Standby State Location
A write to this location places the system into the standby state by halting the main oscillator. It automat-
ically switches the DRAMs to self-refresh if the RFSHEN bit is set in the DRAM Refresh Period register.
All transitions to the standby state are synchronized with DRAM cycles. A write to this location while there
is an active interrupt has no effect.
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