參數(shù)資料
型號(hào)： CL-PS7110-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Low-Power System-on-a-Chip
中文描述： MROM, RISC MICROCONTROLLER, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 49/82頁(yè)
文件大?。?/td> 1101K
代理商： CL-PS7110-VC-A
May 1997
49
DATA BOOK v1.5
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
SQAEN
Sequential access enable. Setting this bit enables sequential accesses that are on a
quad-word boundary to take advantage of faster access times from devices that sup-
port Page mode. The sequential access is faulted after four words, (to allow video
refresh cycles to occur), even if the access is part of a longer sequential access.
CLKEN
Expansion clock enable. Setting this bit enables the EXPCLK to be active during
accesses to the selected expansion device. This provides a timing reference for
devices that need to extend bus cycles using the EXPRDY input. Back-to-back (but
not necessarily Page mode) accesses result in a continuous clock.
See
Chapter 4
for more detail on bus timing.
3.2.15 DRFPR — DRAM Refresh Period Register
The DRAM Refresh Period register is an 8-bit read/write register that enables refresh and selects the
refresh period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the
DRAM refresh period register is
only
cleared by a power on reset that is, the register state is maintained
during a power fail or user reset.
RFSHEN
DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated
by the CL-PS7110 at a rate set by the RFDIV field. Setting this bit also enables Self-
refresh mode when the CL-PS7110 is in the standby state.
Table 3-9.
Values of the Random Access Wait State Field
Value
No. Wait
states
Required Random Access Speed (ns)
00
4
250
01
3
200
10
2
150
11
1
100
Table 3-10. Values of the Sequential Access Wait State Field
Value
No. Wait
States
Required Sequential Random Access
Speed (ns)
00
3
150
01
2
120
10
1
80
11
0
40
7
60
RFSHEN
RFDIV
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