參數(shù)資料
型號(hào)： CL-PS7110-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Low-Power System-on-a-Chip
中文描述： MROM, RISC MICROCONTROLLER, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 58/82頁(yè)
文件大?。?/td> 1101K
代理商： CL-PS7110-VC-A
DATA BOOK v1.5
May 1997
58
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
3.2.28 SYNCIO Synchronous Serial Interface Data Register
SYNCIO is a 16-bit read/write register. The data written to the SYNCIO register configures the SSI, and
the least-significant byte is serialized and transmitted out of the synchronous serial interface to configure
an external ADC, bit D7 (the MSB) first. The transfer clock automatically starts at the programmed fre-
quency, and a synchronization pulse is issued. The ADCIN pin is sampled on every clock edge, and the
result is shifted in to the SYNCIO read register.
During data transfer the SSIBUSY bit is set high, at the end of a transfer the SSEOTI interrupt is asserted.
This interrupt is cleared by reading the SYNCIO register. The data read from the SYNCIO register is the
lastsixteen bits shifted out of the ADC. The length of the data frame can be programmed by writing to the
SYNCIO register, this allows many different ADCs to be accommodated.
Table 3-17
defines the bits in the
SYNCIO register.
3.2.29 STFCLR — Clear All Start Up Reason Flags Location
A write to this location clears all the start-up reason flags in the System Flags Status register (SYSFLG).
3.2.30 BLEOI — Battery Low End of Interrupt
A write to this location clears the interrupt generated by a low battery (falling BATOK with NEXTPWR
high).
12
11/15
73.3%
6.7%
13
4/5
80.0%
8.9%
14
8/9
88.9%
11.1%
15
1
100%
–
Table 3-17. Bits in SYNCIO Write Register
15
24
14
16
13
16
12
8
7
0
Reserved
TXFRMEN
SMCKEN
Frame length
ADC Configuration byte
ADC configuration
8-bit configuration data to be sent to the ADC.
Frame length
The 5-bit Frame length field is the total number of shift clocks required to complete a data transfer.
For many ADCs this is 25, 8 for configuration byte + 1 null bit + 16 bits.
SMCKEN
Setting this bit enables a free-running sample clock at the programmed ADC clock frequency to be
output on the SMPLCK pin.
TXFRMEN
Setting this bit causes an ADC data transfer to be initiated; the value in the ADC configuration field
is shifted out to the ADC, and depending on the frame length programmed, a number of bits is cap-
tured from the ADC. If the SYNCIO register is written to with the TXFRMEN bit low, no ADC trans-
fer occurs, but the Frame length and SMCKEN bits are affected.
Table 3-16. Grayscale Value to Color Mapping
(cont.)
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