參數(shù)資料
型號(hào)： CL-PS7110-VC-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Low-Power System-on-a-Chip
中文描述： MROM, RISC MICROCONTROLLER, PQFP208
封裝： VQFP-208
文件頁數(shù)： 41/82頁
文件大?。?/td> 1101K
代理商： CL-PS7110-VC-A
May 1997
41
DATA BOOK v1.5
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
All internal registers in the CL-PS7110 are reset (cleared to ‘0’) by a system reset (NPOR, NRESET, or
NPWRFL become active), except for the DRAM Refresh Period register (DRFPR), which is only reset
when NPOR becomes active. In addition, the Realtime Clock Data register (RTCDR) and Realtime Clock
Match register (RTCMR) are never reset. This ensures that the DRAM contents and system time are pre-
served through a user reset or power-fail condition.
3.2.1
PADR — Port A Data Register
Values written to this 8-bit read/write register are output on the Port A pins if the corresponding data direc-
tion bits are set
high
(port output). Values read from this register reflect the external state of Port A, not
necessarily the value written to it. All bits are cleared by a system reset.
3.2.2
PBDR — Port B Data Register
Values written to this 8-bit read/write register are output on the Port B pins if the corresponding data direc-
tion bits are set
high
(port output). Values read from this register reflect the external state of Port B, not
necessarily the value written to it. All bits are cleared by a system reset.
8000.0400
PMPCON
RW
12
DC-to-DC Pump Control register
8000.0440
CODR
RW
8
Codec Data I/O register
8000.0480
UARTDR
RW
8
UART FIFO Data register
8000.04C0
UBLCR
RW
32
UART Bit Rate and Line Control register
8000.0500
SYNCIO
RW
16
Synchronous Serial I/O Data register
8000.0540
PALLSW
RW
32
Least-significant 32-bit word of LCD Palette register
8000.0580
PALMSW
RW
32
Most-significant 32-bit word of LCD Palette register
8000.05C0
STFCLR
WR
–
Write to clear all start up reason flags
8000.0600
BLEOI
WR
–
Write to clear Battery Low interrupt
8000.0640
MCEOI
WR
–
Write to clear Media Changed interrupt
8000.0680
TEOI
WR
–
Write to clear Tick and Watchdog interrupt
8000.06C0
TC1EOI
WR
–
Write to clear TC1 interrupt
8000.0700
TC2EOI
WR
–
Write to clear TC2 interrupt
8000.0740
RTCEOI
WR
–
Write to clear RTC Match interrupt
8000.0780
UMSEOI
WR
–
Write to clear UART Modem Status Changed interrupt
8000.07C0
COEOI
WR
–
Write to clear Codec Sound interrupt
8000.0800
HALT
WR
–
Write to enter idle state
8000.0840
STDBY
WR
–
Write to enter standby state
8000.0880–BFFF.FFFF
Reserved
–
–
Write has no effect; read is undefined
Table 3-2.
Internal I/O Memory Locations
(cont.)
Address
Name
R/W
Size
Comments
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