- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379891 > CL-PS7110-VC-A (CIRRUS LOGIC INC) Low-Power System-on-a-Chip PDF資料下載
參數(shù)資料
| 型號(hào)： | CL-PS7110-VC-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 55/82頁 |
| 文件大?。?/td> | 1101K |
| 代理商： | CL-PS7110-VC-A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
May 1997
55
DATA BOOK v1.5
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
3.2.25 UARTDR — UART Data Register
The UARTDR register is an 11-bit read and 8-bit write register for all data transfers to or from the internal
UART.
Data written to this register is pushed onto the 16-byte data Tx holding FIFO if the FIFO is enabled; if not,
it is stored in a 1-byte holding register. This write initiates transmission from the UART.
The UART Data Read register comprises the 8-bit data byte received from the UART together with three
bits of error status. Data read from this register is popped from the 16-byte data Rx FIFO if the FIFO is
enabled, if not it is read from a 1-byte buffer register containing the last byte received by the UART. Data
received and error status is automatically pushed onto the Rx FIFO if it is enabled. The Rx FIFO is 10 bits
wide by 16 deep.
FRMERR
UART framing error. This bit is set if the UART detected a framing error while receiv-
ing the associated data byte. Framing errors are caused by non-matching word
lengths or bit rates.
PARERR
UART parity error. This bit is set if the UART detected a parity error while receiving
the data byte.
OVERR
UART overrun error. This bit is set if more data is received by the UART and the FIFO
is full. The Overrun Error bit is not associated with any single character and so is not
stored in the FIFO, if this bit is set, the entire contents of the FIFO is invalid and should
be cleared. This error bit is cleared by reading the UARTDR register.
3.2.26 UBRLCR — UART Bit Rate and Line Control Register
The UART Bit Rate and Line Control register is a 19-bit read/write register. Writing to this register sets the
bit rate and mode of operation for the internal UART.
Bit rate divisor
This 12-bit field set the bit rate. The bit rate divider is fed by a clock frequency of
3.6864 MHz, it is then further divided internally by 16 to give the bit rate. The formula
to give the divisor value for any bit rate is:
Divisor = (230400 / bit rate) - 1
. A value of
‘0’ in this field is illegal.
Table 3-12
shows some example bit rates with the corre-
sponding divisor value.
10
9
8
7
0
OVERR
PARERR
FRMERR
Rx data
31
19
18
17
16
15
14
13
12
11
0
WRDLEN
FIFOEN
XSTOP
EVENPRT
PRTEN
BREAK
Bit rate divisor
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
| CL-PS7110 | Low-Power System-on-a-Chip |
| CL-PS7111 | Low-Power System-on-a-Chip |
| CL-PS7111-VC-A | Low-Power System-on-a-Chip |
| CL-PS7500FE | System-on-a Chip for Internet Appliance |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7110-VI-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。