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參數(shù)資料
| 型號： | CE5038 |
| 廠商： | Intel Corp. |
| 英文描述： | DVB-S2 Advanced Modulation Satellite Tuner |
| 中文描述： | DVB - S2的先進(jìn)調(diào)制衛(wèi)星調(diào)諧器 |
| 文件頁數(shù)： | 26/41頁 |
| 文件大?。?/td> | 463K |
| 代理商： | CE5038 |
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CE5038
Data Sheet
25
Intel Corporation
3.4.7 RF Bypass Disable (LEN Bit)
The RF bypass function is disabled by setting
LEN
, bit-0 of register byte-4 to a logic ‘1’. By default, this bit is at a
logic ‘0’ at power-up, and therefore the function is enabled. If the function is not required, a power saving of
approximately 15% can be made by setting this bit. See also section 2.3 on page 16.
3.4.8 Output Port Controls (P1 & P0 Bits)
Register bits
P1
and
P0
, bit-7 in register bytes-7 & 5 respectively, control the output port pins, P1 & P0, pin numbers
39 & 24 respectively.
3.4.9 Power Down (PD Bit)
Bit-7 of byte-13 controls the
PD
register bit which is an alternative to the SLEEP pin (see “SLEEP - Pin 11” on
page 20). Setting the
PD
bit to a logic ‘1’ shuts down the analogue sections of the CE5038 effecting a saving of
about 2/3rds of the power required for normal operation. A logic ’0’ restores normal operation. With either hardware
or software power-down, all register settings are unaffected.
3.4.10 Logic Reset (CLR Bit)
Bit-1 of byte-13 controls the
CLR
register bit. When set to a logic ‘1’, this self-clearing bit resets the CE5038 control
logic. Writing a logic ‘0’ has no effect. The following register numbers are reset to their power-on state: 7, 9, 10, 11,
12 & 13. All other register’s contents are unaffected.
Table 12 - Port Control Bits
Bit P1 or P0
Port state
Logic state
(if connected to a pull-up)
0
High impedance
1
(reset state)
1
Low impedance to Vee (Gnd)
0
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