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參數(shù)資料
| 型號： | CE5038 |
| 廠商： | Intel Corp. |
| 英文描述： | DVB-S2 Advanced Modulation Satellite Tuner |
| 中文描述： | DVB - S2的先進調制衛(wèi)星調諧器 |
| 文件頁數(shù)： | 19/41頁 |
| 文件大小： | 463K |
| 代理商： | CE5038 |
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CE5038
Data Sheet
18
Intel Corporation
Figure 11 - Free Running LO Phase Noise Performance
The oscillators are designed to deliver good free running phase noise at 10 kHz offset, therefore the required
integrated phase jitter from the LO can be achieved without the requirement for running with a high comparison
frequency and hence large tuning increment and wide loop bandwidth.
The LO section contains an internal tuning controller, which will automatically tune to the appropriate VCO and sub
band for optimum phase noise performance. The internal LO controller function is transparent to the user and no
user intervention is required. The tuning controller will automatically switch bands when required, however this
function can be disabled with the ‘
VSD
’ bit (see “3.4.15”). This enables the user to select the appropriate VCO and
sub band if required to achieve optimum phase noise performance. For QPSK, automatic mode will be adequate
and should be used. In general for 8 PSK modulation, the automatic mode will also be adequate depending on the
demodulator requirements. 16 QAM may require manual mode to optimize phase noise performance at
frequencies above 1800 MHz.
2.5.1 LO Programming
The controller tunes across the oscillator bands, until lock is achieved. The algorithm for tuning utilises the LO
tuning voltage, Vvar, which is compared at a programmable sample rate against a ‘tune lock’ voltage window and a
‘tune unlock’ voltage window. The sampling rate default on power up is Fcomp/8 however this can be programmed
into further rates through bits LS2-LS0 in byte-10, see “3.4.17” on page 29. The ‘tune lock’ and ‘tune unlock’
windows are set at default values, however, these can be adjusted by bits
WS
,
WH2:0
and
WL2:0
in byte 11, see
“3.4.18” on page 29.
In the event that the controller is unable to find lock the ‘tune lock’ window will be automatically widened. This
facility can be disabled by setting bit
WRE
in byte 11 to logic ‘0’. See 3.4.19 on page 30.
The device has a lock indicator flag,
FL
, which is derived from a time averaged phase comparison between the LO
divider and reference divider inputs to the phase comparator. The
FL
flag is read in the status byte. See 3.3.2 on
page 21.
There is a further hardware lock flag (LOCK output, pin 25; see “3.1.1” on page 20) which generates a logic ‘0’ if the
tuning controller detects the varactor line voltage lies within the ‘tune unlock’ window and if
FL
is set to logic ‘1’. In
other states this output is high impedance.
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
10
100
1000
10000
100000
Frequency offset (log (offset in kHz))
P
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