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參數(shù)資料
| 型號： | CE5038 |
| 廠商： | Intel Corp. |
| 英文描述： | DVB-S2 Advanced Modulation Satellite Tuner |
| 中文描述： | DVB - S2的先進(jìn)調(diào)制衛(wèi)星調(diào)諧器 |
| 文件頁數(shù)： | 22/41頁 |
| 文件大小： | 463K |
| 代理商： | CE5038 |
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CE5038
Data Sheet
21
Intel Corporation
3.3 Read Register
The CE5038 status can be read by addressing the device in its slave transmitter mode by setting the LSB of the
address byte (the R/W bit) to a one. After the master transmits the correct address byte, the CE5038 will
acknowledge its address, and transmit data in response to further clocks on the SCL input. If the master responds
with an acknowledge and further clocks, the status byte will be retransmitted until such time as the master fails to
send an acknowledge, when the CE5038 will release the data bus, allowing the master to generate a stop
condition.
The individual bits in the status register have the following meanings:
3.3.1 Power-On Reset Indicator (POR Bit)
This bit is set to a logic ‘1’ if the VccDIG supply to the PLL section has dropped below typically 3.6 V, e.g., when the
device is initially turned on. The bit is reset to ‘0’ when the read sequence is terminated by a STOP command.
When the POR bit is high, this indicates that the programmed information may have been corrupted and the device
reset to power up condition.
3.3.2 Frequency (& Phase) Lock (FL Bit)
Bit 6 (FL) indicates whether the synthesizer is phase locked, a logic ‘1’ is present if the device is locked and a logic
‘0’ if the device is unlocked.
3.3.3 VCO Sub-Band (SB3:0 Bit)
These bits indicate the vco sub-band value chosen by the LO tuning algorithm when tuning the oscillators
automatically. If manual tuning is used then SB3-SB0 will match bits S3-S0 written to register byte 9 (see “3.4.16”
for sub-band details).
3.3.4 Tune Unlock State (TU1:0 Bit)
These bits define the ‘tune unlock’ window state as below:
See “LO Window Level (WS, WH2:0 & WL2:0 Bits)” on page 29 for further information on the threshold voltages.
Table 4 - Read Data Bit Format (MSB is Transmitted First)
Bit No.
7
(MSB)
6
5
4
3
2
1
0
(LSB)
Address
1
1
0
0
0
MA1
MA0
1
Status
POR
FL
SB3
SB2
SB1
SB0
TU1
TU0
Table 5 - TU1/0 Functions
TU1
TU0
‘Tune unlock’ window state
0
0
Vvar between lower and upper voltage thresholds
0
1
Vvar above upper voltage threshold
1
0
Vvar below lower voltage threshold
1
1
Undefined - do not use
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