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參數(shù)資料
| 型號： | CE5038 |
| 廠商： | Intel Corp. |
| 英文描述： | DVB-S2 Advanced Modulation Satellite Tuner |
| 中文描述： | DVB - S2的先進(jìn)調(diào)制衛(wèi)星調(diào)諧器 |
| 文件頁數(shù)： | 21/41頁 |
| 文件大?。?/td> | 463K |
| 代理商： | CE5038 |
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CE5038
Data Sheet
20
Intel Corporation
All the CE5038 functions are controlled by register bits written through the I2C bus interface. The
SLEEP
pin can be
used to power-down the device, but it can also be put into the power-down mode with the
PD
register bit, the two
functions being logically OR’ed.
Feedback on the status of the CE5038 is provided through eight bits in the status byte register and the phase lock
state is also available on the
LOCK
output pin (as well as the
FL
register bit).
3.0 User Control
3.1 I/O Pins
The I2C interface controls all the major functions. Apart from the various analogue functions, the only pins that
either control the CE5038, or are controlled by the internal logic, are the
LOCK
,
SLEEP
,
P1,
P0
and
ADD
pins.
Details follow:
3.1.1 LOCK - Pin 25
This is an output which indicates phase frequency lock on the correct VCO sub band for optimum phase noise. The
CMOS output can directly drive a low power LED if required.
3.1.2 SLEEP - Pin 11
The
SLEEP
pin shuts down the analogue sections of the device to give a considerable power saving, typically
reducing the power to about one third of its normal level. The RF-bypass function is entirely separate and is
unaffected by the state of this pin. The
SLEEP
pin’s function is OR’ed with the
PD
register bit (see “3.4.9” on
page 25), so that if either is a logic one, the CE5038 will be powered down, or alternatively, both must be at logic
zero for normal operation.
3.1.3 Output Ports, P1 & P0 - Pins 39 & 24
Two open-collector ports are provided for general purpose use, under control of register bits
P1
and
P0
. The default
at power-up is for the
P1
&
P0
register bits to be low, hence the outputs will be off, i.e., in their high-impedance
states. If connected to a pull-up resistor this will therefore result in a logic high. Setting a register bit high will turn
the corresponding output on and therefore pull the logic level to near 0 V giving a logic low.
3.2 Device Address Selection
Two internal logic levels,
MA1
and
MA0
, can be set to one of four possible logic states by the voltage applied to the
ADD
pin (#16). These four states in turn define four different read and write addresses on the I2C bus, so that as
many as four separate devices can be individually addressed on one bus. This is of particular use in a multi-tuner
environment as required by PVR applications.
Table 3 - Address Selection
ADD pin voltage
MA1
MA0
Write Address
Read Address
Hex.
Dec.
Hex.
Dec.
Vee (0 V or Gnd)
0
0
0xC0
192
0xC1
193
Open circuit
0.5 * DIGDEC (±20%)
1
0
1
0xC2
194
0xC3
195
1. can be programmed with a single 30 k
Ω
resistor to DIGDEC
1
0
0xC4
196
0xC5
197
DIGDEC
1
1
0xC6
198
0xC7
199
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