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參數(shù)資料
| 型號： | CE5038 |
| 廠商： | Intel Corp. |
| 英文描述： | DVB-S2 Advanced Modulation Satellite Tuner |
| 中文描述： | DVB - S2的先進調(diào)制衛(wèi)星調(diào)諧器 |
| 文件頁數(shù)： | 20/41頁 |
| 文件大?。?/td> | 463K |
| 代理商： | CE5038 |
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CE5038
Data Sheet
19
Intel Corporation
The tune lock window is centralised within the tuner unlock window. The tuning controller selects the VCO and sub
band so that the varactor voltage is within this window. If this is not possible the lock windows are relaxed
(assuming the WRE bit is set to '1'). The tuning algorithm maintains a level of hysteresis to prevent short term drift
causing switching to an adjacent band.
The LO control logic has provision for master reset to restore initial set up conditions. This is controlled by bit CLR
within data byte 13, see “3.4.10” on page 25.
2.6 PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter to control a varicap tuned LO, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance. The loop can also be operated up to
comparison frequencies of 2 MHz enabling application of a wide loop bandwidth for maximizing the close in phase
noise performance.
The LO input signal is multiplexed from the selected oscillator band to an internal preamplifier, which provides gain
and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully
programmable divider, which is of MN+A architecture. A 16/17 dual modulus prescaler is used.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
the comparison frequency by the reference divider, which is programmable into one of 29 ratios as detailed in
Table 14 on page 26.
The typical application for the crystal oscillator is contained in Figure 2. The output of the phase detector feeds a
charge pump and loop amplifier section. This combined with an external loop filter integrates the current pulses into
the varactor line voltage with an output range of Vee to VccTUNE. The varactor line voltage is externally coupled to
the oscillator section through the input Vvar, enabling application of a third order loop.
Control of the charge pump current can be made in two ways as described in Table 13 on page 26. Either the set
charge pump current can be used at all times, or the charge pump current can be scaled automatically according to
the LO sub-band. The second case allows for reduced loop bandwidth variation as the VCO gain varies with sub-
band.
2.7 Control Logic
The CE5038 is controlled by an I2C data bus and can function as a slave receiver or slave transmitter compatible
with 3V3 or 5 V levels.
Data and Clock are input on the SDA and SCL lines respectively as defined by I2C bus standard. The device can
either accept data (slave receiver, write mode), or send data (slave transmitter, read mode). The LSB of the
address byte (R/W) sets the device into write mode if it is logic ‘0’, and read mode if it is logic ‘1’. Table 4 and Table
7 illustrate the format of the read and write data respectively. The device can be programmed to respond to one of
four addresses, which enables the use of more than one device in an I2C bus system if required for use in PVR
1
systems, for example. Table 3 shows how the address is selected by applying a voltage to the address, ‘
ADD
’,
input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and
during following acknowledge periods after further data bytes are received. When the device is programmed into
read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods
to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
1. PVR - Personal Video Recorder where dual tuners allow the viewer to watch one channel and record another simultaneously, usually to a
hard-disk recording system.
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