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參數(shù)資料
| 型號： | CE5038 |
| 廠商： | Intel Corp. |
| 英文描述： | DVB-S2 Advanced Modulation Satellite Tuner |
| 中文描述： | DVB - S2的先進調(diào)制衛(wèi)星調(diào)諧器 |
| 文件頁數(shù)： | 23/41頁 |
| 文件大?。?/td> | 463K |
| 代理商： | CE5038 |
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CE5038
Data Sheet
22
Intel Corporation
3.4 Write Registers
The CE5038 has twelve registers which can be programmed by addressing the device in its slave receiver mode,
setting the LSB of the address byte (the R/W bit) to a zero. After the master transmits the correct address byte, the
CE5038 will acknowledge its address, and accept data in response to further clocks on the SCL line. At the end of
each byte, the CE5038 will generate the acknowledge bit. The master can at this point, generate a stop condition,
or further clocks on the SCL line if further registers are to be programmed. If data is written after the twelfth register
(byte-13), it will be ignored.
3.4.1 Register Sub-Addressing
If some register bits require changing, but not all, it is not necessary to write to all the registers. The registers can be
addressed in pairs starting with the even numbered bytes, i.e., 2 & 3, 4 & 5, etc. Table 6 below shows the protocol
required to address any of the even numbered register bytes. It therefore follows that to write to register byte-7 for
instance, byte-6 must also be written first. Register pairs may be written in any order, as required by the software,
e.g., 10/11 may be followed by 4/5.
Table 6 - Byte Address Allocation in Write Mode
Data Bits
Byte Selected
7
(MSB)
6
5
4
0
X
X
X
2
1
0
X
X
4
1
1
0
0
6
1
1
0
1
8
1
1
1
0
10
1
1
1
1
12
‘X’
= Don’t care (content defines a register bit).
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