參數(shù)資料
型號: CDB5534U
廠商: Cirrus Logic Inc
文件頁數(shù): 38/43頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR CS5534
標準包裝: 1
ADC 的數(shù)量: 1
位數(shù): 24
采樣率(每秒): 3.84k
數(shù)據(jù)接口: 串行
輸入范圍: 0 ~ 2.5 V
在以下條件下的電源(標準): 35mW @ 5V
工作溫度: -40°C ~ 85°C
已用 IC / 零件: CS5534
已供物品: 板,纜線,CD
相關(guān)產(chǎn)品: CS5534-BSZR-ND - IC ADC 24BIT 4CH W/LNA 24SSOP
CS5534-ASZR-ND - IC ADC 24BIT 4CH W/LNA 24-SSOP
598-1116-5-ND - IC ADC 24BIT 4CH W/LNA 24SSOP
598-1115-5-ND - IC ADC 24BIT 4CH W/LNA 20SSOP
其它名稱: 598-1016
CS5531/32/33/34-AS
DS289F5
43
2.12. Getting Started
This A/D converter has several features. From a
software programmer’s prospective, what should
be done first? To begin, a 4.9152 MHz or
4.096 MHz crystal takes approximately 20 ms to
start. To accommodate for this, it is recommended
that a software delay of approximately 20 ms start
the processor’s ADC initialization code. Next,
since the CS5531/32/33/34 do not provide a power-
on-reset function, the user must first initialize the
ADC to a known state. This is accomplished by re-
setting the ADC’s serial port with the Serial Port
Initialization sequence. This sequence resets the se-
rial port to the command mode and is accomplished
by transmitting 15 SYNC1 command bytes (0xFF
hexadecimal), followed by one SYNC0 command
(0xFE hexadecimal). Once the serial port of the
ADC is in the command mode, the user must reset
all the internal logic by performing a system reset
sequence (see 2.3.2 System Reset Sequence). The
next action is to initialize the voltage reference
mode. The voltage reference select (VRS) bit in the
configuration register must be set based upon the
magnitude of the reference voltage between the
VREF+ and the VREF- pins.
After this, the channel-setup registers (CSRs) should
be initialized, as these registers determine how cali-
brations and conversions will be performed. Once
the CSRs are initialized, the user has three options in
calibrating the ADC: 1) don’t calibrate and use the
default settings; 2) perform self or system calibra-
tions; or 3) upload previously saved calibration re-
sults to the offset and gain registers. At this point,
the ADC is ready to perform conversions.
2.13. PCB Layout
For optimal performance, the CS5531/32/33/34
should be placed entirely over an analog ground
plane. All grounded pins on the ADC, including the
DGND pin, should be connected to the analog
ground plane that runs beneath the chip. In a split-
plane system, place the analog-digital plane split
immediately adjacent to the digital portion of the
chip.
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