參數(shù)資料
型號： CDB5534U
廠商： Cirrus Logic Inc
文件頁數(shù)： 26/43頁
文件大小： 0K
描述： EVAL BOARD FOR CS5534
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 3.84k
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 35mW @ 5V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： CS5534
已供物品： 板，纜線，CD
相關(guān)產(chǎn)品： CS5534-BSZR-ND - IC ADC 24BIT 4CH W/LNA 24SSOP
CS5534-ASZR-ND - IC ADC 24BIT 4CH W/LNA 24-SSOP
598-1116-5-ND - IC ADC 24BIT 4CH W/LNA 24SSOP
598-1115-5-ND - IC ADC 24BIT 4CH W/LNA 20SSOP
其它名稱： 598-1016
CS5531/32/33/34-AS
32
DS289F5
2.5.6. System Calibration
For the system calibration functions, the user must
supply the converter’s calibration signals which rep-
resent ground and full scale. When a system offset
calibration is performed, a ground-referenced signal
must be applied to the converters. Figure 13 illus-
trates system offset calibration.
As shown in Figure 14, the user must input a signal
representing the positive full-scale point to perform
a system gain calibration. In either case, the cali-
bration signals must be within the specified calibra-
tion limits for each specific calibration step (refer
to the System Calibration Specifications).
2.5.7. Calibration Tips
Calibration steps are performed at the output word
rate selected by the WR2-WR0 bits of the channel
setup registers. Due to limited register lengths in
the faster word-rate filters (240 Sps and higher),
channels that are used at these rates should also be
calibrated in one of these word rates, and channels
used in the lower word rates (120 Sps and lower)
should be calibrated at one of these lower rates.
Since higher word rates result in conversion words
with more peak-to-peak noise, calibration should
be performed at the lowest possible output word
rate for maximum accuracy. For the 7.5 Sps to 120
Sps word rate settings, calibrations can be per-
formed at 7.5 Sps, and for 240 Sps and higher, cal-
ibration can be performed at 240 Sps. To minimize
digital noise near the device, the user should wait
for each calibration step to be completed before
reading or writing to the serial port. Reading the
calibration registers and averaging multiple cali-
brations together can produce a more accurate cal-
ibration result. Note that accessing the ADC’s
serial port before a calibration has finished may re-
sult in the loss of synchronization between the mi-
+
_
AIN+
AIN-
1X GAIN
Figure 11. Self-calibration of Offset
AIN+
AIN-
OPEN
+
-
XGAIN
+
-
OPEN
CLOSED
VREF+
CLOSED
VREF-
+
-
Reference
Figure 12. Self-calibration of Gain
+
-
XGAIN
+
-
External
Connections
0V
+
-
AIN+
AIN-
CM +
-
Figure 13. System Calibration of Offset
+
-
XGAIN
+
-
External
Connections
Full Scale +
-
AIN+
AIN-
CM +
-
Figure 14. System Calibration of Gain
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參數(shù)描述
CDB5534U-Z 功能描述:EVAL BD 24-BIT ADCS W/ULTRALN PG 制造商:cirrus logic inc. 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):24 采樣率（每秒）:3.84k 數(shù)據(jù)接口:串行 輸入范圍:±2.5 V 不同條件下的功率（典型值）:35mW @ 3.84kSPS 使用的 IC/零件:CS5534 所含物品:板，電纜 標(biāo)準(zhǔn)包裝:1
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