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參數(shù)資料
| 型號： | CDB5534U |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 19/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR CS5534 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 35mW @ 5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5534 |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | CS5534-BSZR-ND - IC ADC 24BIT 4CH W/LNA 24SSOP CS5534-ASZR-ND - IC ADC 24BIT 4CH W/LNA 24-SSOP 598-1116-5-ND - IC ADC 24BIT 4CH W/LNA 24SSOP 598-1115-5-ND - IC ADC 24BIT 4CH W/LNA 20SSOP |
| 其它名稱： | 598-1016 |
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CS5531/32/33/34-AS
26
DS289F5
2.3.9. Configuration Register Descriptions
PSS (Power Save Select)[31]
0
Standby Mode (Oscillator active, allows quick power-up).
1
Sleep Mode (Oscillator inactive).
PDW (Power Down Mode)[30]
0
Normal Mode
1
Activate the power save select mode.
RS (Reset System)[29]
0
Normal Operation.
1
Activate a Reset cycle. See System Reset Sequence in the datasheet text.
RV (Reset Valid)[28]
0
Normal Operation
1
System was reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read.
IS (Input Short)[27]
0
Normal Input
1
All signal input pairs for each channel are disconnected from the pins and shorted internally.
GB (Guard Signal Bit)[26]
0
Normal Operation of A0 as an output latch.
1
A0’s output is modified to output the common mode output voltage of the instrumentation amplifier (typically
2.5 V). The output latch select bit is ignored when the guard buffer is activated.
VRS (Voltage Reference Select)[25]
0
2.5 V < VREF ≤ [(VA+) - (VA-)]
11 V
≤ VREF ≤ 2.5V
A1-A0 (Output Latch bits)[24:23]
The latch bits (A0 and A1) will be set to the logic state of these bits upon command word execution if the output
latch select bit (OLS) is set. Note that these logic outputs are powered from VA+ and VA-.
00
A0 = 0, A1 = 0
01
A0 = 0, A1 = 1
10
A0 = 1, A1 = 0
11
A0 = 1, A1 = 1
Output Latch Select, OLS[22]
0
When low, uses the Channel-Setup Register as the source of A1 and A0.
1
When set, uses the Configuration Register as the source of A1 and A0.
NU (Not Used)[21]
0
Must always be logic 0. Reserved for future upgrades.
Offset and Gain Select OGS[20]
0
Calibration registers used are based on the CS1-CS0 bits of the referenced Setup.
1
Calibration registers used are based on the OG1-OG0 bits of the referenced Setup.
D31(MSB)
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
PSS
PDW
RS
RV
IS
GB
VRS
A1
A0
OLS
NU
OGS
FRS
NU
D15
D14
D13
D12
D11
D10
D9
D8
D7D6
D5
D4D3D2D1D0
NU
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| CDB5534U-Z | 功能描述:EVAL BD 24-BIT ADCS W/ULTRALN PG 制造商:cirrus logic inc. 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):24 采樣率（每秒）:3.84k 數(shù)據(jù)接口:串行 輸入范圍:±2.5 V 不同條件下的功率（典型值）:35mW @ 3.84kSPS 使用的 IC/零件:CS5534 所含物品:板，電纜 標(biāo)準(zhǔn)包裝:1 |
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