- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17021 > CDB5534U (Cirrus Logic Inc)EVAL BOARD FOR CS5534 PDF資料下載
參數(shù)資料
| 型號： | CDB5534U |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 16/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR CS5534 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標準）： | 35mW @ 5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5534 |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | CS5534-BSZR-ND - IC ADC 24BIT 4CH W/LNA 24SSOP CS5534-ASZR-ND - IC ADC 24BIT 4CH W/LNA 24-SSOP 598-1116-5-ND - IC ADC 24BIT 4CH W/LNA 24SSOP 598-1115-5-ND - IC ADC 24BIT 4CH W/LNA 20SSOP |
| 其它名稱： | 598-1016 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
CS5531/32/33/34-AS
DS289F5
23
2.2.5. Reading/Writing On-Chip Registers
The CS5531/32/33/34’s offset, gain, configuration,
and channel-setup registers are readable and writ-
able while the conversion data register is read only.
As shown in Figure 7, to write to a particular regis-
ter the user must transmit the appropriate write
command and then follow that command by 32 bits
of data. For example, to write 0x80000000 (hexa-
decimal) to physical channel one’s gain register,
the user would first transmit the command byte
0x02
(hexadecimal)
followed
by
the
data
0x80000000 (hexadecimal). Similarly, to read a
particular register the user must transmit the appro-
priate read command and then acquire the 32 bits of
data. Once a register is written to or read from, the
serial port returns to the command mode.
In addition to accessing the internal registers one at
a time, the gain and offset registers as well as the
channel setup registers can be accessed as arrays
(i.e. the entire register set can be accessed with one
command). In the CS5531/32, there are two gain
and offset registers, and in the CS5533/34, there are
four gain and offset registers. There are four chan-
nel setup registers in all parts. As an example, to
write 0x80000000 (hexadecimal) to all four gain
registers in the CS5533, the user would transmit the
command 0x42 (hexadecimal) followed by four it-
erations of 0x80000000 (hexadecimal), (i.e. 0x42
followed
by
0x80000000,
0x80000000, 0x80000000). The registers are writ-
ten to or read from in sequential order (i.e, 1, fol-
lowed by 2, 3, and 4). Once the registers are written
to or read from, the serial port returns to the com-
mand mode.
2.3. Configuration Register
To ease the architectural design and simplify the
serial interface, the configuration register is 32
long, however, only eleven of the 32 bits are used.
The following sections detail the bits in the config-
uration register.
2.3.1. Power Consumption
The CS5531/32/33/34 accommodate three power
consumption modes: normal, standby, and sleep.
The default mode, “normal mode”, is entered after
power
is
applied.
In
this
mode,
the
CS5531/32/33/34
devices
typically
consume
35 mW. The other two modes are referred to as the
power-save modes. They power down most of the
analog portion of the chip and stop filter convolu-
tions. The power-save modes are entered whenever
the power-down (PDW) bit of the configuration
register is set to logic 1. The particular power-save
mode entered depends on state of the PSS (Power
Save Select) bit. If PSS is logic 0, the converter en-
ters the standby mode reducing the power con-
sumption to 4 mW. The standby mode leaves the
oscillator and the on-chip bias generator for the an-
alog portion of the chip active. This allows the con-
verter to quickly return to the normal mode once
PDW is set back to a logic 1. If PSS and PDW are
both set to logic 1, the sleep mode is entered reduc-
ing the consumed power to around 500
W. Since
this sleep mode disables the oscillator, approxi-
mately a 20 ms oscillator start-up delay period is
required before returning to the normal mode. If an
external clock is used, there will be no delay. Fur-
ther note that when the chips are used in the
Gain = 1 mode, the PGIA is powered down. With
the PGIA powered down, the power consumed in
the normal power mode is reduced by approximate-
ly 1/2. Power consumption in the sleep and standby
modes is not affected by the amplifier setting.
2.3.2. System Reset Sequence
The reset system (RS) bit permits the user to per-
form a system reset. A system reset can be initiated
at any time by writing a logic 1 to the RS bit in the
configuration register. After the RS bit has been
set, the internal logic of the chip will be initialized
to a reset state. The reset valid (RV) bit is set indi-
cating that the internal logic was properly reset.
The RV bit is cleared after the configuration regis-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9648-125EBZ | EVAL BOARD AD9648-125 |
| CDB5463U-Z | EVAL BOARD USB FOR CS5463 |
| AD9633-125EBZ | BOARD EVAL FOR AD9633 |
| PM0805-68NK-RC | INDUCTOR CHIP 68NH 10% SMD |
| MAX1379EVKIT+ | EVAL KIT FOR MAX1379 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB5534U-Z | 功能描述:EVAL BD 24-BIT ADCS W/ULTRALN PG 制造商:cirrus logic inc. 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):24 采樣率（每秒）:3.84k 數(shù)據(jù)接口:串行 輸入范圍:±2.5 V 不同條件下的功率（典型值）:35mW @ 3.84kSPS 使用的 IC/零件:CS5534 所含物品:板，電纜 標準包裝:1 |
| CDB5540 | 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR CS5540 - Bulk |
| CDB5541 | 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR 5540 & 5541 N/A - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit For Use |
| CDB5550 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Evaluation Board and Software |
| CDB5560 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Bd 50kSps 24Bit Mux ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。