參數(shù)資料
型號: C3ENPA1-DD
廠商: Motorola, Inc.
元件分類: 網(wǎng)絡(luò)處理器
英文描述: C-3e NETWORK PROCESSOR SILICON REVISION A1
中文描述: ? - 3E的網(wǎng)絡(luò)處理器硅版本格A1
文件頁數(shù): 86/114頁
文件大?。?/td> 746K
代理商: C3ENPA1-DD
86
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
OC-12 Timing Specifications
The OC-12 interface timing is shown in
Figure 18
and described in
Table 43
.
Figure 18
OC-12 Timing Diagram
CPn_1 (TCLKI)
Cycle 1
Cycle 1
Cycle 2
Cycle 3
Cycle 3
Cycle 4
Cycle 5
CPn_0 (TCLK)
CPn+1_2-5 (Tx)
CPn_1 (RCLK)
CPn+2_2-6 (Rx)
CPn+3_2-5 (Rx)
T
c12i
T
c12t
T
c12r
T
c12o
T
c12s
T
c12h
Cycle 2
T
c12d
Table 43
OC-12 Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tc12i
OC-12 Transmit Cycle Time*
*
Input from PHY
Output from C-3e NP
Aligned to TCLK
12.86
ns
Tc12d
OC-3 Clock Duty Cycle
40
60
%
Tc12t
OC-12 Transmit Cycle Time
12.86
ns
Tc12o
OC-12 Output Time
3.0
10.0
ns
Tc12r
OC-12 Receive Cycle Time
12.0
12.86
ns
Tc12s
OC-12 Setup Time
2.0
ns
Tc12h
OC-12 Hold Time
0.0
ns
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