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參數(shù)資料
| 型號(hào)： | C3ENPA1-DD |
| 廠商： | Motorola, Inc. |
| 元件分類： | 網(wǎng)絡(luò)處理器 |
| 英文描述： | C-3e NETWORK PROCESSOR SILICON REVISION A1 |
| 中文描述： | ? - 3E的網(wǎng)絡(luò)處理器硅版本格A1 |
| 文件頁數(shù)： | 22/114頁 |
| 文件大小： | 746K |
| 代理商： | C3ENPA1-DD |
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CHAPTER 1: FUNCTIONAL DESCRIPTION
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
Channel Processors
The C-3e NP contains eight programmable external Channel Processors (CPs) that receive,
process, and transmit network data, plus an additional eight internal CPs that process
data. Typically one CP is assigned to each port for medium bandwidth applications (Fast
Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called
channel
aggregation
in high bandwidth applications (greater than OC-3). Multiple logical ports
can be assigned to a single CP with the addition of an external multiplexor, for low
bandwidth applications, such as DS1 to DS3.
The C-3e NP
’
s architecture supports a variety of industry-standard serial and parallel
protocols and individual port data rates including:
10/100Mb Ethernet (RMII)
1Gb Ethernet (GMII and TBI)
OC-3c
OC-12
100Mbit FibreChannel
DS1/DS3, supported through the use of external framers/multiplexors
The C-3e NP’s programmability can also support a variety of special interfaces, such as
various xDSL encapsulations and proprietary protocols.
Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet
processing and a set of microprogrammable, special-purpose processors, called Serial
Data Processors (SDPs), that provide features such as Ethernet MAC and SONET/SDH
framing, multichannel HDLC, and ATM cell delineation. This means you usually only need
to include PHYs to complete the system.
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| C3ENPA1-DS | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:C-3e NETWORK PROCESSOR SILICON REVISION A1 |
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