參數(shù)資料
型號： C3ENPA1-DD
廠商： Motorola, Inc.
元件分類： 網(wǎng)絡(luò)處理器
英文描述： C-3e NETWORK PROCESSOR SILICON REVISION A1
中文描述： ? - 3E的網(wǎng)絡(luò)處理器硅版本格A1
文件頁數(shù)： 45/114頁
文件大?。?/td> 746K
代理商： C3ENPA1-DD
Pin Descriptions Grouped by Function
45
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-3e NP to communicate
through external logic to PROM. The PROM clock is
1
/
2
to
1
/
16
the core clock rate.The
maximum PROM size addressable is 4MBytes, and must use a
“
by 16
”
part. The PROM
signals are listed in
Table 17
.
Figure 5
shows the connections between the PROM Interface and external board logic.
The application is required to provide an external shift register with parallel-in and
parallel-out capabilities, and a parallel load register. Both devices should be
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
Table 17
PROM Interface Signals
SIGNAL
NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
SPDO
Y5
1
LVTTL
O
Serial Data Out
SPDI
Y6
1
LVTTL
I
PD
O
Serial Data In
SPLD
Y7
1
LVTTL
When load is asserted on a positive clock
edge, the external logic performs a parallel
load. On each positive clock edge when
load is de-asserted, the shift registers shift.
When the PROM interface is idle:
if SPLD is asserted HI it indicates low
speed serial protocol,
if asserted LOW it indicates MDIO serial
protocol.
SPCK
Y8
1
LVTTL
O
Clock
TOTAL PINS
4
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