參數(shù)資料
型號: C3ENPA1-DD
廠商: Motorola, Inc.
元件分類: 網(wǎng)絡處理器
英文描述: C-3e NETWORK PROCESSOR SILICON REVISION A1
中文描述: ? - 3E的網(wǎng)絡處理器硅版本格A1
文件頁數(shù): 47/114頁
文件大?。?/td> 746K
代理商: C3ENPA1-DD
Pin Descriptions Grouped by Function
47
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
8
SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the
network processor internal shift register.
9
SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the
network processor PROM_RETURN_DATA register.
Figure 6
PROM Interface Timing Outline
SPCLK
SPLD
1
2
4
5
6
7
8
9
11
10
12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15 16 17 18
20
19
21 22 23
1
2
3
4
5
6
7
x
A
20
A
19
A
18
SPDTO
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
The PROM_ADDR is loaded into the
The PROM_ADDR is shifted into
(SPCLK Rising Edge used for shifting)
2
The PROM_ADDR is loaded into the
external presentation register.
The PROM_DATA is
The PROM_DATA is loaded into the
external shift register.
The PROM_DATA is shifted into the C-5's
Internal shift register.
The PROM_DATA is loaded into the C-5's
internal PROM_RETURN_DATA register.
SPDTI
x
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
x
x
x
x
x
x
XP PROM Interface outline
XP PROM Interface detail
SPLD
SPDTO
SPDTI
`
`
A1
A2
`
`
A3
A4
A5
D1
D2
D3
D1
D2
A1
A2
A3
A4
1
3
4
5
6
7
8
9
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