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參數(shù)資料
| 型號： | C3ENPA1-DD |
| 廠商： | Motorola, Inc. |
| 元件分類： | 網(wǎng)絡(luò)處理器 |
| 英文描述： | C-3e NETWORK PROCESSOR SILICON REVISION A1 |
| 中文描述： | ? - 3E的網(wǎng)絡(luò)處理器硅版本格A1 |
| 文件頁數(shù)： | 31/114頁 |
| 文件大?。?/td> | 746K |
| 代理商： | C3ENPA1-DD |
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Pin Descriptions Grouped by Function
31
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
Clock Signals
Table 6
describes the C-3e NP clock signals.
CP Interface Signals
The C-3e NP
’
s 8 external CPs support various network physical interfaces, providing a
serial interface to the PHY layer. Interfaces are configured via bits in the C-3e NP register
set. Many interfaces are possible by programming the configuration registers. CPs can be
used individually or in a cluster (four CPs) to implement the various interfaces.
Table 7
provides a quick reference of all the CP pins organized by clusters. There are seven
physical I/O pins associated with each CP All pins are capable of receiving data, with some
configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can
be configured as differential pairs for LVPECL compatibility.
In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally
configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four
CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for
receive and four for transmit) or four CPs that share the transmit and receive functions for
non-wire speed applications.
During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial
Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the
SDPs, with each getting access to the necessary I/O pins.
Table 6
Clock and Reference Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
SCLK*
SCLKX*
*
SCLK and SCLKX must not be AC-coupled.
If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must
be wired to an external reference, as specified in
Table 34
on page 73. If none of the CPs are configured for
LVPECL operation, then the CPREF pin can be left unconnected.
F14
F15
1
1
LVPECL
LVPECL
I
I
Core Clock Rate (Differential)
CCLK0
F16
1
LVTTL
I
PD
I
PD
I
PD
I
PD
I
PD
Programmable CP Clock Input
CCLK1
E16
1
LVTTL
Programmable CP Clock Input
CCLK2
E15
1
LVTTL
Programmable CP Clock Input
CCLK3
E14
1
LVTTL
Programmable CP Clock Input
CPREF
D16
1
LVPECL
Reference
TOTAL
7
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