參數(shù)資料
型號： BX80525U700256E
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 700 MHz, MICROPROCESSOR, XMA
文件頁數(shù)： 47/102頁
文件大?。?/td> 878K
代理商： BX80525U700256E
Datasheet
49
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
NOTES:
1. These values are specified at nominal VCCCORE for the processor core and nominal VCCL2/VCC3.3 for the L2
cache (if applicable).
2. Processor power includes the power dissipated by the processor core, the L2 cache, and the AGTL + bus
termination. The maximum power for each of these components does not occur simultaneously.
3. TJUNCTIONOFFSET is the worst-case difference between the thermal reading from the on-die thermal diode
and the hottest location on the processor’s core.
4. Power density is the maximum power the processor die can dissipate (i.e. processor power) divided by the
die area over which the power is generated.
5. Power for these processors is generated over the entire processor die (see Figure 40 for processor die
dimensions).
6. Power for these processors is generated over the core area (see Figure 20 for processor die and core area
dimensions). Thermal solution designs should compensate for this smaller heat flux area (core) and not
assume that the power is uniformly distributed across the entire die area (core + cache).
7. TJUNCTION offset values do not include any thermal diode kit measurement error. Diode kit measurement
error must be added to the TJUNCTION offset value from the table, as outlined in the Intel Pentium III
processor Thermal Metrology for CPUID-068h Family Processors. Intel has characterized the use of the
Analog Devices AD1021 diode measurement kit and found its measurement error to be 1 °C.
Table 26. Thermal Specifications for S.E.C.C.2 Packaged Processors1
Proc.
Core
Freq.
(MHz)
L2
Cache
Size
(Kbytes)
Proc.
Power 2
(W)
Proc.
Core
Power
(W)
L2
Cache
Power
(W)
Power
Density4
(W/cm2)
Max
TJUNCTION
(°C)
TJUNCTION
Offset3
(°C)
L2 Cache
Min TCASE
(°C)
L2 Cache
Max TCASE
(°C)
Min
TCOVER
(°C)
Max
TCOVER
(°C)
450
512
25.3
1.26
21.65
90
4.8
5
105
5
75
500
512
28.0
1.33
23.95
90
4.8
5
105
5
75
533B
512
29.7
1.37
25.45
90
4.8
5
105
5
75
533EB
256
17.6
17.4
N/A
24.26
82
2.67
N/A
5
75
550
512
30.8
1.37
26.35
80
4.8
5
105
5
75
550E
256
18.2
18.0
N/A
25.16
82
2.67
N/A
5
75
600
512
34.5
1.60
29.55
85
4.8
5
105
5
75
600B
512
34.5
1.60
29.55
85
4.8
5
105
5
75
600E
256
19.8
19.6
N/A
27.36
82
2.97
N/A
5
75
600EB
256
19.8
19.6
N/A
27.36
82
2.97
N/A
5
75
650
256
21.5
21.3
N/A
29.56
82
3.17
N/A
5
75
667
256
22.0
21.8
N/A
30.56
82
3.27
N/A
5
75
700
256
23.1
22.9
N/A
31.86
80
3.37
N/A
5
75
733
256
24.1
23.9
N/A
33.26
80
3.57
N/A
5
75
750
256
24.7
24.5
N/A
34.06
80
3.77
N/A
5
75
800
256
26.4
26.2
N/A
36.46
80
3.87
N/A
5
75
800EB
256
26.4
26.2
N/A
36.46
80
3.87
N/A
5
75
Figure 20. Processor Functional Die Layout (CPUID 068xh)
Cache Area
0.05 in
2
0.362”
0.292”
0.170”
0.448”
Core Area
0.11 in2
Die Area
0.16 in2
Die Area = 1.05 cm2
Cache Area = 0.32 cm
2
Core Area = 0.73 cm2
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