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參數(shù)資料
| 型號： | BX80525U700256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 700 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 25/102頁 |
| 文件大小： | 878K |
| 代理商： | BX80525U700256E |
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Datasheet
29
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel Pentium III processor frequencies.
2. These values are specified at the processor core pins.
3. These values are specified at the processor edge fingers.
4. Parameter measured at 14 mA (for use with TTL inputs).
5. Leakage current affects input, output and I/O signals.
6. (0
≤ V
IN ≤ 2.5 V +5%).
7. (0
≤ V
OUT ≤ 2.5 V +5%).
8. This specification applies to the Pentium III processor with CPUID=067xh.
9. This specification applies to the Pentium III processor with CPUID=068xh.
10.Parameters apply to all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD.
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the VTT voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called VREF.
Table 11 lists the nominal specification for the AGTL+ termination voltage (VTT). The AGTL+
reference voltage (VREF) is generated on the processor substrate for the processor core, but should
be set to 2/3 VTT for other AGTL+ logic using a voltage divider on the baseboard. It is important
that the baseboard impedance be specified and held to a ±15% tolerance, and that the intrinsic trace
capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on
the GTL+ buffer specification, see the Pentium
II Processor Developer's Manual (Order Number
243502) and AP-585, Pentium II Processor GTL+ Guidelines (Order Number 243330).
Table 10. Non-AGTL+ Signal Group DC Specifications 1
Symbol
Parameter
Min
Max
Unit
Notes
VIL
Input Low Voltage
–0.30
–0.15
–0.30
–0.15
0.5
0.7
0.5
0.7
V
3, 8
3, 9, 10
2, 9; BCLK only
2, 9; PICCLK only
2, 9; PWRGOOD only
VIH
Input High Voltage
1.7
2.0
2.625
V
3, 8
3, 9, 10
2, 9; BCLK, PICCLK,
and PWRGOOD only
VOL
Output Low Voltage
0.4
0.5
V
3, 4, 8
3, 4, 9
VOH
Output High Voltage
N/A
2.625
V
All outputs are open-
drain
IOL
Output Low Current
14
mA
3
IL
Leakage Current
±100
A
5, 6, 7
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