參數(shù)資料
型號(hào)： BX80525U700256E
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 700 MHz, MICROPROCESSOR, XMA
文件頁(yè)數(shù)： 16/102頁(yè)
文件大?。?/td> 878K
代理商： BX80525U700256E
20
Datasheet
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
voltage regulator is stable. This will prevent the possibility of the processor supply going above the
specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-
DC converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. A resistor of greater than or equal to 10 k
may be used to connect the VID signals to the
converter input.
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VCCL2/
VCC3.3, VSS, or to any other signal (including each other) can result in component malfunction or
incompatibility with future Pentium III processors. See Section 5.5 for a pin listing of the processor
and the location of each RESERVED pin.
All TESTHI pins must be connected to 2.5 V via 1 k
-10 k pull-up resistor.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each
APIC data line.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused AGTL+ inputs should be left as no connects; AGTL+ termination is provided
on the processor. Unused active low CMOS inputs should be connected through a resistor to 2.5 V.
Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
For unused pins, it is suggested that ~10 k
resistors be used for pull-ups (except for PICD[1:0]
discussed above), and ~1 k
resistors be used as pull-downs.
2.8
Processor System Bus Signal Groups
In order to simplify the following discussion, the Pentium III processor system bus signals have
been combined into groups by buffer type. All Pentium III processor system bus outputs are open
drain and require a high-level source provided externally by the termination or pull-up resistor.
However, the Pentium III processor includes on-cartridge (CPUID 067xh) or on-die (CPUID
068xh) termination.
AGTL+ input signals have differential input buffers, which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term “AGTL+ Input” refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output”
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
EMI pins may be connected to baseboard ground and/or to chassis ground through zero ohm (0
)
resistors. The 0
resistors should be placed in close proximity to the SC242 connector. The path to
chassis ground should be short in length and have a low impedance.
The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5 V. The CMOS,
APIC, and TAP outputs are open drain and should be pulled high to 2.5 V. This ensures not only
correct operation for current Pentium III processors, but compatibility with future Pentium III
processors as well.
The groups and the signals contained within each group are shown in Table 4. Refer to Section 7.0
for a description of these signals.
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