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參數(shù)資料
| 型號(hào)： | BX80525U700256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 700 MHz, MICROPROCESSOR, XMA |
| 文件頁(yè)數(shù)： | 19/102頁(yè) |
| 文件大小： | 878K |
| 代理商： | BX80525U700256E |
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Datasheet
23
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Pentium III processor be first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect to the rest of the
chain unless one of the other components is capable of accepting a 2.5 V input. Similar
considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be
required with each driving a different voltage level.
The Debug Port should be placed at the start and end of the TAP chain with the TDI of the first
component coming from the Debug Port and the TDO from the last component going to the Debug
Port. In a 2-way MP system, be cautious when including an empty SC242 connector in the scan
chain. All connectors in the scan chain must have a processor installed to complete the chain or the
system must support a method to bypass the empty connectors; SC242 terminator substrates should
not connect TDI to TDO in order to avoid placing the TDO pull-up resistors in parallel. See SC242
Terminator Card Design Guidelines (Order Number 243409) for more details.
Figure 5. BSEL[1:0] Example for a 100/133 MHz Capable System
(100 MHz Processor Installed)
Figure 6. BSEL[1:0] Example for a 100/133 MHz Capable System
(133 MHz Processor Installed)
Processor
Core
GND
1
Κ
3.3
Κ
System
Shutdown
Logic
3.3V
220
BSEL0
S
C
2
4
2
133/100#
CK133
3.3V
220
BSEL1
0
0
Intel Pentium III Processor
Processor
Core
GND
1
Κ
3.3
Κ
System
Shutdown
Logic
3.3V
220
BSEL0
S
C
2
4
2
133/100#
CK133
3.3V
220
BSEL1
1
Κ
3.3
Κ
Intel Pentium III Processor
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