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參數(shù)資料
| 型號： | BX80525U667256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 35/102頁 |
| 文件大?。?/td> | 878K |
| 代理商： | BX80525U667256E |
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38
Datasheet
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
3.0
Signal Quality Specifications
Signals driven on the Pentium III processor system bus should meet signal quality specifications to
ensure that the components read data properly and to ensure that incoming signals do not affect the
long term reliability of the component. Specifications are provided for simulation and
measurement at the processor core; they should not be tested at the edge fingers.
The AGTL+ and non-AGTL+ signal quality specifications listed in this section apply to
Pentium III processors with CPUID=068xh. It is recommended that these specifications be used
with Pentium III processors with CPUID=067xh, however any deviations from these guidelines
must be verified with the specifications listed in the Pentium II Processor Developer's Manual
(Order Number 243502).
3.1
BCLK, PICCLK, and PWRGOOD Signal Quality
Specifications and Measurement Guidelines
Table 19 describes the signal quality specifications at the processor core for the Pentium III
processor system bus clock (BCLK), APIC clock (PICCLK), and PWRGOOD signals. Figure 14
describes the signal quality waveform for the system bus clock at the processor core pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 19. BCLK, PICCLK, and PWRGOOD Signal Quality Specifications at the
Processor Core 1
V# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: VIN Absolute Voltage Range
–0.7
3.3
V
14
V2: Rising Edge Ringback
2.0
V
14
2
V3: Falling Edge Ringback
0.5
0.7
V
14
2
3
Figure 14. BCLK and PICCLK Generic Clock Waveform
V2
V1
V3
T6/T26
T5/T25
T4/T24
V4
V5
T3/T23
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