參數(shù)資料
型號(hào)： BX80525U667256E
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, MICROPROCESSOR, XMA
文件頁數(shù)： 13/102頁
文件大?。?/td> 878K
代理商： BX80525U667256E
18
Datasheet
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
plane segment with a 1-ounce plating. Bulk decoupling for the large current swings when the part
is powering on, or entering/exiting low power states, is provided on the voltage regulation module
(VRM). If using Intel’s enabled VRM solutions see developer.intel.com for the specification and a
list of qualified vendors. The VCCCORE input should be capable of delivering a recommended
minimum dIccCORE/dt (defined in Table 8) while maintaining the required tolerances (also defined
in Table 8).
2.4.2
Processor System Bus AGTL+ Decoupling
The Pentium III processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system baseboard for proper AGTL+ bus
operation. See AP-906, 100 MHz AGTL+ Layout Guidelines for the Pentium III Processor and
Intel 440BX AGPset (Order Number 245086) or the appropriate platform design guide, AP-907,
Pentium III Processor Power Distribution Guidelines (Order Number 245085), and the GTL+
buffer specification in the Pentium
II Processor Developer's Manual (Order Number 243502) for
more information.
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the Pentium III processor system bus
interface. All Pentium III processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the P6 Family of Processors Hardware Developer's Manual
(Order Number 244001) for further details.
2.6
Voltage Identification
There are five voltage identification pins on the SC242 connector. These pins can be used to
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines
the voltage required by the processor core. The VID pins are needed to cleanly support voltage
specification variations on current and future Pentium III processors. VID[4:0] are defined in
Table 3. A ‘1’ in this table refers to an open pin and a ‘0’ refers to a short to ground. The power
supply must supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future Pentium III processors, the range of values in
bold in Table 3 should be supported. A smaller range will risk the ability of the system to migrate
to a higher performance Pentium III processor and/or maintain compatibility with current
Pentium III processors.
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