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參數(shù)資料
| 型號： | BX80525U667256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 30/102頁 |
| 文件大小： | 878K |
| 代理商： | BX80525U667256E |
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Datasheet
33
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.7 V at the processor core
pins. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. When driven inactive or after VCCCORE, VCCL2/VCC3.3, and BCLK become stable.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V (CPUID 067xh) or 0.75 V (CPUID 068xh) at
the processor core pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into a 150
load pulled up to 2.5 V +5%.
7. This specification applies to the Pentium III processor with CPUID=067xh.
8. This specification applies to the Pentium III processor with CPUID=068xh.
Table 15. System Bus AC Specifications (CMOS Signal Group) at the
Processor Core Pins
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2BCLKs
8
Active and Inactive
states
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
8, 11
5
Table 16. System Bus AC Specifications (Reset Conditions) 1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Setup Time
4BCLKs
10
Before deassertion
of RESET#
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
220
BCLKs
10
After clock that
deasserts RESET#
Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Core Pins 1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T21: PICCLK Frequency
2.0
33.3
MHz
T22: PICCLK Period
30.0
500.0
ns
7
T23: PICCLK High Time
12.0
ns
7
T24: PICCLK Low Time
12.0
ns
7
T25: PICCLK Rise Time
0.25
3.0
ns
7
T26: PICCLK Fall Time
0.25
3.0
ns
7
T27: PICD[1:0] Setup Time
8.0
5.0
ns
9
4,7
4, 8
T28: PICD[1:0] Hold Time
2.5
ns
9
4
T29: PICD[1:0] Valid Delay
1.5
10
ns
8
4, 5, 6, 7
T29a: PICD[1:0] Valid Delay (Rising Edge)
1.5
8.7
ns
8
4, 5, 6, 8
T29b: PICD[1:0] Valid Delay (Falling Edge)
1.5
12.0
ns
8
4, 5, 6, 8
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