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參數(shù)資料
| 型號： | BX80525U667256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 24/102頁 |
| 文件大?。?/td> | 878K |
| 代理商： | BX80525U667256E |
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28
Datasheet
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
6. VTT must be held to 1.5 V ±9%. It is recommended that VTT be held to 1.5 V ±3% while the Pentium III
processor system bus is idle. This is measured at the processor edge fingers across a 20 MHz bandwidth.
7. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the
bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops (and
impedance discontinuities) across the connector, processor edge fingers, and to the processor core.
VCCCORE must return to within the static voltage specification within 100 s after a transient event; see the
VRM 8.2 DC-DC Converter Design Guidelines (Order Number 243773) for further details.
8. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. VCCCORE must return to within the static voltage
specification within 100
s after a transient event.
9. VCCL2/VCC3.3 and ICCL2/ICC3.3 supply the second level cache (“Discrete” cache type only). Unless otherwise
noted, this specification applies to all Pentium III processor cache sizes. Systems should be designed for
these specifications, even if a smaller cache size is used.
10.Max ICC measurements are measured at VCC max voltage, maximum temperature, under maximum signal
loading conditions. The Max Icc currents specified do not occur simultaneously under the stress
measurement condition.
11. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VCCCORE
(VCCCORE_TYP). In this case, the maximum current level for the regulator, IccCORE_REG, can be reduced from
the specified maximum current IccCORE _MAX and is calculated by the equation:
IccCORE_REG = IccCORE_MAX × VCCCORE_TYP / (VCCCORE_TYP + VCCCORE Tolerance, Transient)
12.The current specified is the current required for a single Pentium III processor. A similar amount of current is
drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended
termination is used (see Section 2.1).
13.The current specified is also for AutoHALT state.
14.Maximum values are specified by design/characterization at nominal VCCCORE and nominal VCCL2/VCC3.3.
15.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
16.dICC/dt specifications are measured and specified at the SC242 connector pins.
17.Vcc5 and ICC5 are not used by the Pentium III processors. The VCC5 supply is used for the test equipment
and tools.
18.This specification applies to the Pentium III processor with CPUID=067xh.
19.This specification applies to the Pentium III processor with CPUID=068xh.
20.Max ICC measurements are measured at VCC nominal voltage, maximum temperature, under maximum
signal loading conditions. The Max Icc currents specified do not occur simultaneously under the stress
measurement condition.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processor frequencies.
2. VIH and VOH for the Pentium III processor may experience excursions up to 200 mV above VTT for a single
system bus clock. However, input signal drivers must comply with the signal quality specifications in Section
3.0.
3. Minimum and maximum VTT are given in Table 11.
4. Parameter correlated to measure into a 25
resistor terminated to 1.5 V.
5. IOH for the Pentium III processor may experience excursions of up to a 12 mA for a single bus clock.
6. Leakage current affects input, output, and I/O signals.
7. (0
≤ V
IN ≤ 2.0 V +5%).
8. (0
≤ V
OUT ≤ 2.0 V +5%).
9. Refer to the Pentium III I/O Buffer Models for I/V characteristics.
10.(0
≤ V
IN ≤ 1.5 V +5%).
11. (0
≤ V
OUT ≤ 1.5 V +5%).
12.This specification applies to the Pentium III processor with CPUID=067xh.
13.This specification applies to the Pentium III processor with CPUID=068xh.
Table 9.
AGTL+ Signal Groups DC Specifications 1, 4, 5
Symbol
Parameter
Min
Max
Unit
Notes
VIL
Input Low Voltage
–0.30
–0.15
0.82
VREF - 0.20
V
12
13
VIH
Input High Voltage
1.22
VREF + 0.20
VTT
V
2, 3, 12
2, 3, 13
Ron
Buffer On Resistance
16.67
9
IL
Leakage Current
±100
A
6, 7, 8, 12
6, 10, 11, 13
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