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參數(shù)資料
| 型號： | BX80525U667256E |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 102/102頁 |
| 文件大?。?/td> | 878K |
| 代理商： | BX80525U667256E |
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Datasheet
99
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates
their L1 and L2 caches without writing back any of their contents. RESET# must
remain active for one microsecond for a “warm” Reset; for a power-on Reset,
RESET# must stay active for at least one millisecond after VCCCORE and CLK have
reached their proper specifications. On observing active RESET#, all processor
system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the P6
Family of Processors Hardware Developer’s Manual (Order Number 244001) for
details.
The processor may have its outputs tristated via power-on configuration.
Otherwise, if INIT# is sampled active during the active-to-inactive transition of
RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not
BIST is executed, the processor will begin program execution at the power on
Reset vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate pins
of all processor system bus agents.
RP#
I/O
The RP# (Request Parity) signal is driven by the request initiator, and provides
parity protection on ADS# and REQ[4:0]#. It must connect the appropriate pins of
all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. This definition allows parity to be high
when all covered signals are high.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RSP#
I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
SLOTOCC#
O
The SLOTOCC# signal is defined to allow a system design to detect the presence
of a terminator card or processor in a SC242 connector. Combined with the VID
combination of VID[4:0]= 11111 (see Section 2.6), a system can determine if a
SC242 connector is occupied, and whether a processor core is present. See the
table below for states and values for determining the type of cartridge in the SC242
connector.
Table 41. Signal Description (Continued)
Name
Type
Description
SC242 Occupation Truth Table
Signal
Value
Status
SLOTOCC#
VID[4:0]
0
Anything other
than ‘11111’
Processor with core in SC242 connector.
SLOTOCC#
VID[4:0]
0
11111
Terminator cartridge in SC242 connector
(i.e., no core present).
SLOTOCC#
VID[4:0]
1
Any value
SC242 connector not occupied.
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