參數(shù)資料
型號(hào)： BX80525U667256E
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, MICROPROCESSOR, XMA
文件頁(yè)數(shù)： 27/102頁(yè)
文件大小： 878K
代理商： BX80525U667256E
30
Datasheet
Pentium III Processor for the SC242 at 450 MHz to 800 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Pentium III processors contain AGTL+ termination resistors at the end of each signal trace on the processor
substrate. Pentium III processors generate VREF on the processor substrate by using a voltage divider on
VTT supplied through the SC 242 connector.
3. VTT must be held to 1.5 V ±9%; dICCVTT/dt is specified in Table 8. It is recommended that VTT be held to
1.5 V ±3% while the Pentium III processor system bus is idle. This is measured at the processor edge
fingers.
4. RTT must be held within a tolerance of ±5%
5. VREF is generated on the processor substrate to be 2/3 VTT ±2% nominally.
2.13
System Bus AC Specifications
The Pentium III processor system bus timings specified in this section are defined at the Pentium III
processor core pads. Unless otherwise specified, timings are tested at the processor core during
manufacturing. See Section 7.0 for the Pentium III processor edge connector signal definitions. See
Section 5.6 for the Pentium III processor closest accessible core pad to substrate via assignment.
Table 12 through Table 18 list the AC specifications associated with the Pentium III processor
system bus. These specifications are broken into the following categories: Table 12 through
Table 13 contain the system bus clock core frequency and cache bus frequencies, Table 14 contains
the AGTL+ specifications, Table 15 contains the CMOS signal group specifications, Table 16
contains timings for the Reset conditions, Table 17 covers APIC bus timing, and Table 18 covers
TAP timing.
All Pentium II processor system bus AC specifications for the AGTL+ signal group are relative to
the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’
logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Pentium III processor in Viewlogic XTK model format (formerly known as QUAD format) as
the Pentium III Processor I/O Buffer Models on Intel’s Developer’s Website
(http://developer.intel.com.) AGTL+ layout guidelines are also available in AP-906, 100 MHz
AGTL+ Layout Guidelines for the Pentium III Processor and Intel 440BX AGPset (Order
Number 245086) or the appropriate platform design guide.
Care should be taken to read all notes associated with a particular timing parameter.
Table 11. AGTL+ Bus Specifications 1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
VTT
Bus Termination Voltage
1.365
1.50
1.635
V
3
RTT
Termination Resistor
56
4
VREF
Bus Reference Voltage
0.95
2/3 VTT
1.05
V
5
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