參數(shù)資料
型號(hào)： BU-66318G0-110
廠商： DATA DEVICE CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 278K
代理商： BU-66318G0-110
17
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
1
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PCI memory read from ACE registers/memory with no DRR pending & FIFO empty
produces Retry. Master should attempt read as soon as possible (preferably within 33 clocks).
3rd read produces disconnect with data, DRR complete
AA
A
D
6h
0ns
250ns
500ns
750ns
I
PCICLK
IO
AD[31:0]
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
FIGURE 8. PCI READ OF ACE MEMORY/REGISTER
1 2 3 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
DAT3
A DAT1 DAT2
DAT4
DAT5 DAT6
DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15
DAT16
0ns
500ns
1000ns
1
PCICLK
AD
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
FIGURE 9. PCI WRITE BURST TO ACE MEMORY WITH FIFO EMPTY
FIGURE 9 illustrates a 16 Dword (32 word) PCI memory write
burst, with the write FIFO empty (or with enough free space to
absorb the 16 Dwords in the FIFO). The write FIFO accepts PCI
memory writes to the ACE memory (BAR0) and ACE registers
(BAR1 offset 00h - FCh). It does not accept writes to the PCI
interface registers at BAR1 offset 800-81Ch. Writes to the BAR1
800-81Ch space go directly into the PCI interface registers. The
32 byte write shown could be an entire 1553 message being writ-
ten to ACE memory.
Writes into the BAR 0 space must be word or Dword. If only one
byte enable is asserted in a word, the PCI Enhanced Mini-ACE
terminates the transaction with a Target-Abort.
Writes into the BAR 1 00-FCh space must be word or Dword. If
only one byte enable is asserted in a word, the PCI Enhanced
Mini-ACE terminates the transaction with a Target-Abort. Since
the ACE registers in this space are really 16-bit registers packed
into the lower word of a 32-bit structure, only lower word or
Dword writes transfer bits into these ACE registers.
In addition, as per PCI spec, a Memory Write and Invalidate
(C/BE[3:0]# = Fh) command will be aliased to the basic Memory
Write command and the timing diagram would look the same as
FIGURE 4.
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