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參數(shù)資料
| 型號： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 278K |
| 代理商： | BU-66318G0-110 |
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Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
TABLE 27. PCI BUS ADDRESS AND DATA SIGNALS
SIGNAL NAME
PIN
DESCRIPTION
AD31 (MSB) (I/O)
12
AD30 (I/O)
14
AD29 (I/O)
16
AD28 (I/O)
17
AD27 (I/O)
18
AD26 (I/O)
19
AD25 (I/O)
22
AD24 (I/O)
23
AD23 (I/O)
26
AD22 (I/O)
32
AD21 (I/O)
36
AD20 (I/O)
43
AD19 (I/O)
45
AD18 (I/O)
46
AD17 (I/O)
62
AD16 (I/O)
63
32-Bit PCI Bus Address / Data lines. Address and Data are multiplexed on the same pins. Each bus opera-
tion consists of an address phase followed by one or more data phases.
Address phases are identified when the control signal FRAME# is asserted. Data transfers occur during
those clock cycles in which the control signals IRDY# and TRDY# are both asserted.
Bus Command and Byte Enables. These signals are multiplexed on the same pins. During the address
phase of a bus operation, these pins identify the bus command, as shown in the table of ACE-Bridge com-
mands below. During the data phase of a bus operation, these pins are used as Byte Enables, with
C/BE[0]# enabling byte 0 (LSB) and C/BE[3]# enabling byte 3 (MSB).
C/BE[3:0]#
Description (during address phase)
0
1
0
Memory Read
0
1
Memory Write
1
0
1
0
Configuration Read
1
0
1
Configuration Write
1
0
Memory Read - MULTIPLE
Parity. This signal is even parity across the entire AD[31:0] field along with the C/BE[3:0]# field. The parity
is stable in the clock following the address phase and is sourced by the Bus Master. During the data phase
for write operations, the Bus Master sources this signal on the clock following IRDY# active. During the
data phase for read operations, this signal is sourced by the Target and is valid on the clock following
TRDY# active. The PAR signal therefore has the same timing as AD[31:0], delayed by one clock.
AD15 (I/O)
64
AD14 (I/O)
65
AD13 (I/O)
85
AD12 (I/O)
87
AD11 (I/O)
92
AD10 (I/O)
94
AD9 (I/O)
95
AD8 (I/O)
111
AD7 (I/O)
114
AD6 (I/O)
115
AD5 (I/O)
121
AD4 (I/O)
147
AD3 (I/O)
165
AD2 (I/O)
166
AD1 (I/O)
167
AD0 (I/O) (LSB)
168
C/BE[3]# (I)
24
C/BE[2]# (I)
37
C/BE[1]# (I)
84
C/BE[0]# (I)
148
PAR(I/O)
35
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