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參數(shù)資料
| 型號(hào)： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 278K |
| 代理商： | BU-66318G0-110 |
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13
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
TABLE 18. TIMER CONTROL / INTERRUPT REGISTER
(WRITE 81CH)
BIT
DESCRIPTION
31 (MSB)
0
6
0
5
LOAD DISCARD TIMER
4
INCREMENT DISCARD TIMER
3
LOAD FAILSAFE TIMER
2
DECREMENT FAILSAFE TIMER
1
CLEAR FAILSAFE INTERRUPT
0 (LSB)
NOTE: All REG7 functions occur when a '1' is written to the correspon-
ding bit.
ACE RESET
LOAD DISCARD TIMER: (for test purposes with the value
stored in REG5).
INCREMENT DISCARD TIMER: (for test purposes).
LOAD FAILSAFE TIMER: (for test purposes with the value
stored in REG3).
DECREMENT FAILSAFE TIMER: (for test purposes).
CLEAR FAILSAFE INTERRUPT: Writing a "1" will clear the fail-
safe error irq and resume normal operation.
ACE RESET: Writing a "1" to REG7 will generate a reset pulse
to the ACE's.
BAR2 is used to access the 128 Kbytes (64K words) of Local
RAM, if present. BAR2 returns FFFE0000h when all Fs are writ-
ten to it.
PCI BUS OPERATIONS
The basic ACE-Bridge PCI transaction takes 3 PCI clocks, on top
of the command phase. For example, a single write to any loca-
tion within the ACE-Bridge memory space takes 4 PCI clocks, as
shown in FIGURE 4. Note that this is a single write, not an
attempted burst write: FRAME# is not held asserted by the mas-
ter. Also note that a write to the ACE registers or ACE memory
is actually a write into the write FIFO whereas a write to the PCI
interface registers (BAR1 800-81Ch) is a write to the registers
themselves.
1
2
3
4
5
6
7
PCI single write to any legal memory location (C/BE# = 7h)
ADRS
DATA
7h
Byte Enables
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
FIGURE 4. PCI SINGLE MEMORY WRITE TO ACE-BRIDGE
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