參數(shù)資料
型號(hào)： BU-66318G0-110
廠商： DATA DEVICE CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 278K
代理商： BU-66318G0-110
6
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
INTRODUCTION
The BU-66318 ACE-Bridge comprises a complete integrated
interface between a PCI bus and up to six Enhanced Mini-ACE,
Mini-ACE, Mini-ACE Mark3, or Micro-ACE series MIL-STD-1553
terminals. Note that the term "ACE" is used extensively in this
document and can apply to any of the four generations of part
series, unless a specific part series is mentioned, such as the
Enhanced Mini-ACE series. The BU-66318 also includes an
interface between the PCI bus and a local microprocessor and
shared RAM. The local processor/RAM interface does not have
to be used and can be disabled easily. The BU-66318 may be
used to configure one to six MIL-STD-1553 terminals.
The ACE-Bridge is a fully compliant target agent, as defined by
the PCI Local Bus Specification Revision 2.2, using a 32 bit inter-
face that operates at clock speeds of up to 33 Mhz, from a 3.3V
signaling bus. It supports both PCI and Local CPU / ACE inter-
rupts and contains a 32 deep, double word wide FIFO that han-
dles PCI burst write transfer cycles. The BU-66318 comes pack-
aged in a low profile 208 pin 1.1 square inch package.
The BU-66318 contains only a single set of configuration regis-
ters so that all of the ACE hybrid memory and register space may
be addressed through a single PCI function. Internal registers
keep track of how many ACE devices are connected to the local
bus, indicate if a local CPU is present, control the Subsystem
Vendor and Device ID, enable/disable interrupts, and control the
Fail-Safe operation of the device. There is also a 32-bit register
available for general purpose use.
There are three Base Address Registers utilized to implement
ACE memory space (BAR0), register space (BAR1), and local
RAM space (BAR2). Base Address Register mapping is con-
tained in PCI configuration register space.
For designs without a local bus processor, the register func-
tion/mapping presented to driver software is very similar to that
provided by DDC's Enhanced Mini-ACE based PCI cards (BU-
65569i, for example), so that drivers for these cards can be used
with very little or no modification. The Enhanced Mini-ACE reg-
ister and memory mapping is the same as that in the BU-65569i.
The PCI-ACE interface control registers in the BAR1800-81Ch
space are a superset of the BU-65569i and contain extra inter-
rupt enable bits.
The ACE register mapping is located in PCI memory space,
allowing for full PCI access to all 1553 terminals. Although the
BU-66318 can be accessed in 32-bit words, all ACE registers are
internally accessed in 16 bit word reads / writes. If a 32-bit read
is performed from the PCI bus in ACE register space the lower
word contains the ACE register and the upper word is all zeroes.
ACE memory is also accessed internally in 16-bit words, but
memory is accessed sequentially allowing for 32-bits of data to
be read from the PCI bus. In other words, if a 32-bit PCI read is
performed the first 16 bits of data would be read from the
requested address, the next 16 bits of data would be read from
the initial ACE memory address + 1. The BU-66318 supports 32-
bit and 16-bit read and write operations only, 8-bit writes are ille-
gal, and 8-bit reads will return 16-bit data.
NUMBER OF ACE CHANNELS
An internal register keeps track of how many ACE devices are
attached to the BU-66318, along with whether a local micro-
processor is present. The ACE's are detected by the use of the
INT (interrupt) signals. If an interrupt line is tied low on power-up
that channel is defined as not populated. When a PCI reset sig-
nal occurs (RST#), a Master Clear is issued to all ACE devices.
The BU-66318 will then poll all six ACE interrupt inputs and
record their status. All unused INT signals should be grounded
so as to indicate channel population.
LOCAL MICROPROCESSOR
The local microprocessor is detected via the GNT signal. When
a PCI reset signal occurs (RST#), the BU-66318 will poll the
GNT signal. If the GNT signal is tied low on power-up, the BU-
66318 determines no processor to be present. It is very impor-
tant to note that whether a local CPU is found or not will control
if the local bus signals are to be tri-stated.
LOCAL BUS INTERFACE
A local bus interface is available on the ACE-Bridge device.
When the local bus interface is not used, the user must tie the
GNT input signal low in order to bypass the local bus mode.
When the local bus interface is used, the MEM/REG, RD/WR,
ADDRESS, DATA and SELECT buses will be tri-stated unless
the bus is granted to the Bolt-On-PCI device. The bus will be
granted when the ACE-Bridge receives a GNT back. The bus will
remain in control of the ACE-Bridge device until ACK and GNT
both go high. The ACK signal will be asserted low when the Bolt-
On-PCI device has control of the bus signals. If the local bus
interface is not used all control signals are two-state, not tri-state.
In addition, the ACE-Bridge provides the local bus signals, CS
and B_RDY, to the local processor to allow read/write access by
the local processor to the ACE-Bridge internal registers.
INTERRUPTS
PCI Interrupts are generated on the INTA# output signal to the
host bus. The interrupts from each ACE and local CPU, if used,
are functionally or'd together to provide a single interrupt. ACE
hybrids should be programmed to generate level mode interrupts
to the ACE-Bridge. Interrupts may be sent through the PCI bus
to the local bus processor (if present) by the use of the "Interrupt
Vector From PCI" control register contained in BAR1. Writing to
this location from the PCI bus causes a local CPU interrupt. A
read from this location by the local CPU will clear the register.
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