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參數(shù)資料
| 型號： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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TABLE 20. MIN/MAX DELAYED READ FORMULAS
TYPE OF READ
MIN TIME FORMULA
MAX TIME FORMULA
ACE memory
(BAR0), double
word
13 x PCI_CLKperiod
+ 11 x ACE_CLKperiod
16 x PCI_CLKperiod
+ 14 x ACE_CLKperiod
TABLE 21. ADDITIONAL DRR DELAY FOR
CONTESTED ACE RAM ACCESS
ACE OPERATING MODE
MAX ADDITIONAL ACE
CLOCKS
Enhanced CPU access enabled, single
word transfer
3
Enhanced CPU access enabled, double
word transfer
6
Enhanced CPU access disabled, single
word transfer
67
Enhanced CPU access disabled, double
word transfer
Enhanced CPU access is a feature of the Enhanced Mini-ACEs and
Micro-ACEs ONLY and is controlled by bit 14 of Configuration Register
#6.
74
10 x PCI_CLKperiod
+ 6 x ACE_CLKperiod
3 x PCI_CLKperiod
ACE memory
(BAR0) single
word or ACE reg-
ister (BAR1, dou-
ble word or lower
word)
No CBEN# assert-
ed or ACE register
(BAR1) upper
word
8 x PCI_CLKperiod
+ 5 x ACE_CLKperiod
3 x PCI_CLKperiod
The third case returns all zeroes and is shown only for com-
pleteness.
The following examples have the same conditions: PCI clock =
33MHz, ACE clock = 16MHz, no ACE contention.
Single word read
Min time = 8 x 30 ns + 5 x 62.5 ns = 552.5 ns
Max time = 10 x 30ns + 6 x 62.5 ns = 675 ns
Double word read
Min time = 13 x 30 ns + 11 x 62.5 ns = 1077.5 ns
Max time = 16 x 30ns + 14 x 62.5 ns = 1167.5 ns
In addition, the following amount of ACE clocks should be added
for maximum time if the ACE is active.
Note that one of the conditions for enquing a DRR is that the
write FIFO must be empty. Theoretically, for efficient use of PCI
bus bandwidth, the driver software should be written such that it
checks the FIFO condition (BAR1 800-81CH registers are direct-
ly readable, bypassing the DRR mechanism) before reading
from the other ACE-Bridge locations. If the FIFO is not empty
(BAR1 800h bit 30 is the FIFO not empty flag) and a read is
attempted, the bus master will be using PCI bandwidth repeating
the read request while the FIFO empties, before the read
request is actually enqued as a DRR in the ACE-Bridge. The
FIFO "drain" delay will increase the overall read delay further.
A typical situation where the extra FIFO "drain" delay might be
encountered is during diagnostics of the internal RAM. When a
RAM pattern is written to the device the FIFO can fill completely
and the readback of the pattern might occur immediately after the
pattern is written. In this case, the first read attempt will produce a
retry which will cause the master to start repeating the read
request. AFTER the FIFO drains fully the next repeated read
request will actually cause the ACE-Bridge to enque the read
request, which will start the DRR mechanism described earlier.
The FIFO drain speed is dependent upon the ACE clock and
how full the FIFO is. On average, a 16MHz ACE clock can drain
a 16 bit word from the FIFO every ~600nS. For example, if the
FIFO is full when a PCI read is attempted, the read will complete
in ~ (32 x 0.6s) + 1 s = 20.2s.
This delay is something to be aware of when using the ACE-
Bridge with PCI bridges/controllers that have PCI retry counters.
Examples of such devices for the PPC environment are the
CPC710, GT-64260, etc. If the retry counters are enabled in
these devices the value should be set to a large enough value so
that the counter does not reach the maximum value when read-
ing from the ACE-Bridge. Typically, the power-on default value
is on these devices is 0, which will defeat the counter and allows
infinite retries.
The minimum retry period is determined by how quickly the ACE-
Bridge terminates a transaction and the PCI rule that a master
"must deassert REQ# for two consecutive clocks, one of which
while the bus is Idle, before any transaction that was target ter-
minated can be repeated". The ACE-Bridge terminates a PCI
transaction in 5 clocks, as shown in FIGURE 8. The "deassert
REQ#" rule involves the bus arbiter during bus reacquisition by
the master.
Actual measurements of a PCI-Enhanced Mini-ACE being read
by the PCI motherboard host in a hi-performance X86 system
(not the timing shown in FIGURE 8) show that a read can be
retried every 8 PCI clocks. Since it is the motherboard PCI con-
troller, the arbiter parks the PCI bus on this controller, which
allows such fast retry speeds.
Therefore, in this extreme case, the motherboard host can
repeat the read 84 times (20.2s/(8x30ns)) before data is pre-
sented, so the PCI retry counter should be set to a value higher
than 84.
16
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
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