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參數(shù)資料
| 型號： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁數(shù)： | 32/32頁 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
For typical non-local bus processor applications the only PCI-ACE
interface control registers (BAR1 + 800-81Ch) that must be
accessed by driver software are the first two registers. These reg-
isters contain the following critical functions: the 800h register
indicates how many ACEs are present and which ACEs are inter-
rupting and the 804h register enables interrupts for specific ACEs.
For typical applications, the other registers or other bits within the
800 and 804 registers can be left at their default values.
Because ACE registers cannot meet PCI bus latency requirements
directly, the BAR1 ACE register space (BAR1 000-5FCh) is read
via "delayed read requests" and the FIFO is used for writes.
TABLE 8. (BAR1) ACE/ CONTROL REGISTERS - 4K BYTE TOTAL SPACE
ADDRESS OFFSET
000-0FC
100-1FC
200-2FC
300-3FC
400-4FC
500-5FC
NAME
ACE1
ACE2
ACE3
ACE4
ACE5
ACE6
800
ACE-PCI INTERFACE CONTROL REGISTERS
REG0
804
REG1
808
REG2
80C
REG3
810
REG4
814
REG5
818
REG6
81C
REG7
TYPE
R
R/W
R
R/W
R
R/W
W
BITS
15-0
31-16
31-0
DEFINITION / ACCESSIBILITY
ACE 1 REGISTER SPACE
Register Accesses are on a 32-bit boundary. Last 2 bits of PCI
address dropped to form ACE Address.
0
15-0
ACE 3 Register Space (if ACE 3 present)
15-0
ACE 2 Register Space (if ACE 2 present)
0
15-0
ACE 4 Register Space (if ACE 4 present)
0
15-0
ACE 5 Register Space (if ACE 5 present)
0
15-0
ACE 6 Register Space (if ACE 6 present)
Note: If an access is attempted in an ACE REGISTER space
where the ACE is not present, the access will be terminated with a
target abort.
GLOBAL ACTIVITY
FAIL-SAFE OPERATION / INTERRUPT
FAIL-SAFE TIMER
FAIL-SAFE TIMER VALUE
DISCARD TIMER
DISCARD TIMER VALUE
RESERVED
TIMER CONTROL / INTERRUPT
The "ACE-PCI interface control registers" (BAR1 800-81Ch) are
part of the PCI interface portion of the die and are written and
read directly from the PCI bus, without use of the write FIFO or
delayed read request logic.
ACE REGISTER SPACE (ACE1 - ACE6): This address space
allows access to ACE registers. Each 252-byte segment of allo-
cated address space allows access to a total of 64 ACE registers
per segment. Register access is on a 32-bit boundary (E.G.
BAR1 + 000 = ACE1 REG 0, BAR1 + 004 = ACE 1 REG 1, BAR1
+ 008 = ACE 1 REG 2, etc).
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