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參數(shù)資料
| 型號： | BU-66318G0-110 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, LQFP-208 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大小： | 278K |
| 代理商： | BU-66318G0-110 |
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7
Data Device Corporation
www.ddc-web.com
BU-66318
B-09/05-0
REGISTER AND MEMORY ADDRESSING
The BU-66318 ACE-Bridge contains a set of "Type 00h" PCI
configuration registers that are used to map the device into the
host system. The PCI configuration register space is mapped in
accordance with PCI revision 2.2 specifications.
PCI COMMAND REGISTER
Reserved: These bits are read-only and return zeroes when
read.
SERR# Enable: This is an enable bit for the SERR# driver. A
value of 0b disables the driver. A value of 1b enables the driver.
The value after RST# is 0b.
Parity Error Control: This bit controls the device's response to
parity errors. When the bit is 1b, the device will take its normal
action when a parity error is detected. When this bit is 0b, the
TABLE 2. BU-66318 CONFIGURATION REGISTER SPACE
ADDRESS
31
24
23
16
15
8
70
00h
Device ID(0401h)
Vendor ID(4DDCh)
04h
Status Register
Command Register
08h
Class Code = 078000 h
Rev ID = 02
0Ch
BIST(not implemented)(00h)
Header Type(00h)
Latency Timer,Not Used
(00h)
Cache Line SizeNot Used
(00h)
10h
Base Address Register 0 (for ACE memory)
14h
R/W
Base Address Register 1 (for ACE registers)
R/W
R/W and 0's, see text
00h
R/W
R/W and 0's, see text
00h
18h
Base Address Register 2 (for local RAM) 128K byte window
1Ch-24h
Base Address Registers 3 through 5 (not used) 00000000h
28h
Card Bus CIS pointer (not used) 00000000h
2Ch
Subsystem Device and Subsystem Vendor IDUser configurable (see text)
30h
Expansion ROM Base Address (Not Used, bit 0 = 0)
34h-38h
Reserved(0000h)
3Ch
Max Lat.
00h
Min Gnt
00h
Interrupt Pin
01h
Interrupt Line
R/W
TABLE 3. PCI COMMAND REGISTER
BIT
DESCRIPTION
15:10
Reserved, 0s
9
8
0
SERR# Enable
7
0
6
Parity Error Control
5:2
0
1
Memory Space
0 (LSB)
0
TABLE 4. PCI STATUS REGISTER
BIT
DESCRIPTION
31
Detected Parity Error
30
29:28
Signaled System Error
0
27
Signaled Target Abort
26:25
DEVSEL# Timing = 01 (medium)
24
0
23
Fast Back-to-Back Capable = 1
22:21
0
20:16
Reserved, 0s
device will ignore any parity errors that it detects and continue
normal operation. The value after RST# is 0b.
Memory Space: This bit controls the device's response to mem-
ory space accesses. A value of 0b disables the device response.
A value of 1b allows the device to respond to memory space
accesses. The value after RST# is 0b.
PCI STATUS REGISTER
This register records status information for PCI bus related
events. Reads to this register behave normally, but writes can
only reset bits. A bit is reset whenever the register is written and
the data in the corresponding bit location is a 1.
Detected Parity Error: The device will set this bit whenever it
detects a parity error, even if the Parity Error Control bit in the
PCI Control register is 0b.
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