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參數(shù)資料
| 型號： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標準包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應(yīng)商設(shè)備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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11
RETIMER function. The device may be set to respond to any
one of four DEVAD values, (4, 5, 30 or 31) by controlling the
level on the MFC and MFD pins at the end of reset. These
pins are normally outputs, but become inputs when RSTN is
active, and so may be pulled to the desired value by
moderate value resistors (~5k
), which will not affect the
normal operation of the pins when outputs. The value on
these pins will be latched at the rising edge of RSTN. The
coding is shown in Table 3-5. A weak pullup is built into
these pins, so that if unwired, they will default to DEVAD = 5.
See Table 6-13 and Figure 6-9 for the timing of these
signals. The Clause 45-accessible registers are listed in
Table 3-7. These register addresses are independent of the
DEVAD value, including the ‘Vendor Defined’ DEVAD values
30 & 31; thus registers 30.8 & 31.8 include the RX_FAULT
and TX_FAULT bits.
Each individual device may have up to 216 (65,536)
registers. The BBT3420 implements 11 of the IEEE-defined
registers for PHY XS and DTE XS devices (they may be
accessed identically through any of the implemented DEVAD
address values), and 11 of the 32k (215) allowed Vendor
Specific registers. The latter have been placed in the block
beginning at C000’h so as to avoid the areas currently
defined as for use by the XENPAK module and similar MSA
devices, to facilitate use of the BBT3420 in systems using
such modules and/or devices.
In order to align the registers and bits as closely as possible
to the new IEEE Clause 45 standard, while maintaining
compatibility with previous versions of the part before the
Clause 45 interface was defined, which used only the
Clause 22 interface, the control and status bits are differently
distributed among the registers in the two formats. The
Clause 22 registers are listed in Table 3-6, and the Clause
45 registers in Table 3-7.
TABLE 3-6. MDIO REGISTERS IN CLAUSE 22 FORMAT
MII REGISTERS
ADDRESS
NAME
DESCRIPTION
DEFAULT
R/W
DETAILS
00’h
Control
Reset, Enable serial loop back mode.
2040’h
R/W
01’h
Status
Device Present & LOS
800F’h (Note 2) RO
02:3’h
ID Code
Manufacturer and Device OUI & IDs
01839C5V’h
RO
See (Note 1)
04’h
Speed Ability
10Gbps Ability
0001’h
RO
05’h
IEEE Devices
Devices in Package, Clause 22 capable
0021’h (Note 3) RO
06’h
Vendor Devices
Vendor Specific Devices in Package
0000’h (Note 3) RO
08’h
Fault Status
Transmit & Receive Fault
8000’h (Note 2) RO/LH
10’h
Misc. Control 1
Channel, Comma, TX Idle, MF controls
00C0’h
R/W
11’h
Misc. Control 2
Code, Comma, Codec, TCx controls
0140’h
R/W
12’h
Special Control Register DC Offset & RC[A:D] phase shift control
0000’h
R/W
13’h
Resvd2
Spare Status
0000’h
RO
16’h
ERROR
Sets XGMII ERROR Code
0FF’h
R/W
17’h
Loop Back
Controls Serial & Parallel Loopback
0000’h
R/W
18’h
Receive Clock
Receive Clock Mode
0001’h
R/W
19’h
Symbol
IDLE, Alignment and Elasticity Control
000F’h
R/W
1A’h
Errors
Error Flags
0000’h (Note 2) RO
1B’h
XGMII IDLE
XGMII-side IDLE Code
0007’h
R/W
1C’h
Boost/Pre-emp
Boost and Pre-emphasis Control
0000’h
R/W
1D’h
Misc. Control 3
VDDQ, LOS, RC timing, /A/K/R/
0000’h
R/W
1E’h
Internal Test
AAAA’h
R/W
1F’h
Half Rate
Half-rate clock mode enable
0000’h
R/W
NOTES:
1. ‘V’ is a version number. See under “3.15 JTAG” on page 22 for a note about the version number.
2. Read value depends on status signal values. Value shown indicates ‘normal’ operation.
3. Read value depends on DEVAD setting, see Table 3-5 and Figure 6-9 for details.
BBT3420
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