3.15 JTAG Five pins – TMS, TCK, TDO, TRST, and TDI – support IEEE Standard 1149.1 JTAG testing. The JTAG test capability has been implem" />
參數(shù)資料
型號(hào)： BBT3420-SN
廠商： Intersil
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 0K
描述： TXRX QUAD MULTI-RATE 289-EBGA
標(biāo)準(zhǔn)包裝： 84
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： XAUI，XGMII，MDC/MDIO
電源電壓： 1.7 V ~ 1.9 V
安裝類型： 表面貼裝
封裝/外殼： 289-BGA
供應(yīng)商設(shè)備封裝： 289-BGA（19x19）
包裝： 托盤
22
3.15 JTAG
Five pins – TMS, TCK, TDO, TRST, and TDI – support IEEE
Standard 1149.1 JTAG testing. The JTAG test capability has
been implemented on all signal pins except the high-speed
differential output and input terminals. The following
boundary scan operation codes are supported:
3.15.1 Manufacturers ID
The Manufacturers ID Code returned when reading the ID
Code from the JTAG pins is as follows:
V0005351’h,
Where ‘V’ is an internal 4-bit version number. Consult the
Contact Information resources on Page 44 for information as
to the meaning of the revision number.
3.15.2 BIST Operation
The Built-In Self Test (BIST) function will only operate
correctly if the Encoder/Decoder is enabled (the CODE pin,
see Table 4-6, is high, and the CODECENA bit, see Table 3-
16 and/or Table 3-32, is set), trunking is turned off to avoid
loss of characters to channel alignment, by taking the
PSYNC pin low (also see Table 3-22 and/or Table 3-32), and
the pseudo-random AKR generation is disabled via the
AKR_EN bit, see Table 3-28 and/or Table 3-33. The Pseudo-
Random Bit Sequence (PRBS) pattern generator puts out an
8-bit byte-wide pattern, whose length is either 223-1 bytes, or
13458 bytes, depending on the value of the SHRT_BIST bit;
see Table 3-16 and/or Table 3-33. Either the BIST_EN bit
(Table 3-16 and/or Table 3-33) or the BISTEN pin (see
Table 4-6 on page 26) causes each Serial Transmitter to put
out a sequence of several commas (typically 9), followed by
the PRBS pattern as 8-bit data, the sequence then repeating
indefinitely, and causes each Serial Receiver to search its
incoming bit stream for the same pattern. Once the comma
group has set the byte alignment, the BIST error detector will
be enabled, and the decoded pattern will then be checked.
Any bit error will set the error detector for the corresponding
channel. These detectors may be monitored via the MF[A:D]
pins (see Table 4-6) and via the MDIO system (see Table 3-
25). The detectors may be reset by using SOFT_RESET
(see Table 3-28 and/or Table 3-34). The full 223-1 byte
pattern takes approximately 27ms at 3.125Gbps. Note that
certain characterization tests (including generated jitter) can
be performed using the PRBS generator, with the 8b/10b
Encoder/Decoder disabled, since this will generate a greater
variety of Inter Symbol Interference (ISI) patterns than
encoded data. However, the checking circuitry will not
accept the data as error-free, since the raw pattern will
contain many false apparent comma patterns, causing
frequent byte realignments, etc.
TABLE 3-34. SOFT RESET CONTROL REGISTER 3 (CLAUSE 45)
MII REGISTER 49167, ADDRESS = C00F’h
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15
SOFT_RESET
Write 1 to initiate. 0’b
R/W SC
Reset the entire chip except MII register
settings
14:0
Reserved
TABLE 3-35. JTAG OPERATIONS
INSTRUCTION
CODE
Extest
0000
Sample/Preload
0001
HighZ
0010
Clamp
0011
ID Code
0100
Bypass
1111
UDR0
1000
UDR1
1001
RunBIST
1010
BBT3420
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