4 Pin Specifications for BBT3420 The BBT3420 device is packaged in a 289-pin HSPBGA. The terminals are grouped in tables by functionalit" />
參數資料
型號: BBT3420-SN
廠商: Intersil
文件頁數: 16/38頁
文件大小: 0K
描述: TXRX QUAD MULTI-RATE 289-EBGA
標準包裝: 84
類型: 收發(fā)器
驅動器/接收器數: 4/4
規(guī)程: XAUI,XGMII,MDC/MDIO
電源電壓: 1.7 V ~ 1.9 V
安裝類型: 表面貼裝
封裝/外殼: 289-BGA
供應商設備封裝: 289-BGA(19x19)
包裝: 托盤
23
4 Pin Specifications for BBT3420
The BBT3420 device is packaged in a 289-pin HSPBGA. The terminals are grouped in tables by functionality.
TABLE 4-1. CLOCK PINS
PIN#
NAME
TYPE
DESCRIPTION
J3, J2
RFCP/RFCN
Input
Differential Reference Input Clock
A10
TCA
Input
Transmit Data Clock, Channels A. The data on TDA(0 - 9) islatched on the rising
and falling edges of TCA. When PSYNC is high, TCA acts as the transmit clock for
all channels.
F16, M16, U10
TCB, TCC,
TCD
Input
Transmit Data Clock, Channels B - D. When PSYNC is low, the data on TDx(0 - 9)
is latched on the rising and falling edges of the transmit clocks. When PSYNC is
high, these pins are ignored.
A11
RCA
Output
Receive Data Clock, Channels A. The data on RDA(0 - 9) is output on the rising and
falling edges of RCA. When PSYNC is high, RCA acts as the receive clock for all
channels.
F17, M17, U11
RCB, RCC,
RCD
Output
Receive Data Clock, Channels B - D. When PSYNC is low, the data on RDx(0 - 9)
is output on the rising and falling edges of the receive clocks. When PSYNC is high,
these pins are undefined.
TABLE 4-2. SERIAL SIDE DATA PINS
PIN#
NAME
TYPE
DESCRIPTION
D5, D6, F4, G4, M4, L4, P5,
P6
TXAP/TXAN
TXBP/TXBN
TXCP/TXCN
TXDP/TXDN
Output
Transmit Differential Pairs, Channel A - D. CML high-speed serial outputs.
B5, B6, F2, G2, M2, L2,T5, T6 RXAP/RXAN
RXBP/RXBN
RXCP/RXCN
RXDP/RXDN
Input
Receive Differential Pairs, Channel A - D. CML high-speed serial inputs.
TABLE 4-3. PARALLEL SIDE DATA PINS
PIN#
NAME
TYPE
DESCRIPTION
C8, B8, A8, E9, D9, C9,
E10, D10
TDA(0-7)
Input
Transmit Data Pins, Channel A. Parallel data on this bus is clocked on the rising and
falling edges of TCA.
C10
TDA8
Input
Transmit Data/ K-code Flag, Channel A. When CODE is low, this pin is the 9th bit of an
8b10b-encoded/10b-encoded byte to be transmitted. When CODE is high, this pin acts
as the K-character generator indicator. When high, this pin causes the data on TDA(0-
7) to be encoded into a K-character. Data on this pin is clocked on the rising and falling
edges of TCA.
B10
TDA9
Input
Transmit Data Pin, Channel A. When CODE is low, this pin is the 10th bit of an 8b/10b-
encoded byte. When CODE is high, this pin is undefined. Data on this pin is clocked on
the rising and falling edges of TCA.
C11, B11, E12, D12,
C12, C13, B13, A13
RDA(0-7)(0-7)
Output
Receive Data Pins, Channel A. Parallel data on this bus is valid on the rising and falling
edges of RCA.
B14
RDA8
Output
Receive Data/ K-code Flag, Channel A. When CODE is low, this pin is the 9th bit of a
received 8b/10b-encoded byte. When CODE is high, this pin acts as the K-character
flag. When high, this indicates the data on RDA(0-7) is a valid K-character. Data on this
pin is valid on the rising and falling edges of RCA.
A14
RDA9
Output
Receive Data Pin/ Error Detect, Channel A. When CODE is low, this pin is the 10th bit
of an 8b/10b-encoded byte. When CODE is high, this pin goes high to signify the
occurrence of either a parity error or an invalid code word during the decoding of the
received data. Data on this pin is valid on the rising and falling edges of RCA.
BBT3420
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